74HC595 8-Bit Serial-In / Parallel-Out Shift Register
8-bit serial-input / parallel-output shift register with 3-state outputs. Data is clocked in serially on SRCLK, then latched to the output pins on a rising edge of RCLK. Commonly chained for expanding digital outputs over SPI.
Aliase:SN74HC595N, 74595, 74HCT595, SIPO Shift Register
DIP-16 Top View
16 Pins
Pinout Table16
| Pin | Signal / Name | Type | Alternative Functions |
|---|---|---|---|
| 1 | QB | Digital | Parallel Output Bit 1 (3-state) |
| 2 | QC | Digital | Parallel Output Bit 2 (3-state) |
| 3 | QD | Digital | Parallel Output Bit 3 (3-state) |
| 4 | QE | Digital | Parallel Output Bit 4 (3-state) |
| 5 | QF | Digital | Parallel Output Bit 5 (3-state) |
| 6 | QG | Digital | Parallel Output Bit 6 (3-state) |
| 7 | QH | Digital | Parallel Output Bit 7 (3-state) |
| 8 | GND | Ground | System Ground (0V) |
| 9 | QH' | Digital | Serial Cascade Output (connect to SER of next 74HC595 in chain) |
| 10 | ~SRCLR | Digital | Shift Register Clear (Active Low — pull LOW to clear shift register; tie HIGH if unused) |
| 11 | SRCLK | Digital | Shift Register Clock (rising edge shifts SER data into register) |
| 12 | RCLK | Digital | Storage Register Clock / Latch (rising edge transfers shift register to output latches) |
| 13 | ~OE | Digital | Output Enable (Active Low — pull LOW to enable QA–QH; HIGH = all outputs Hi-Z) |
| 14 | SER | Digital | Serial Data Input (clocked in on rising edge of SRCLK) |
| 15 | QA | Digital | Parallel Output Bit 0 (first in, 3-state) |
| 16 | VCC | Power | Positive Power Supply (2–6V) |