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Module2024SGeT e.V.

OSM Size-M (Rev. 1.2) Pinout

SGeT Open Standard Module (OSM) V1.2 Size-M (Medium, 30×45 mm) pinout specification with 476 LGA solder contacts featuring dual eDP, UFS, PCIe, triple Ethernet and advanced I/O.

Aliase:OSM, Open Standard Module, OSM Size-M, OSM-M, OSM-MF, OSM-ME, SGeT OSM, Size Medium
SGeT OSM Specification V1.2 (PDF)SGeT e.V. Standardization Group

OSM Size-M (30×45mm)

476 Pins
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data input port A (I CMOS, VCC_OUT_IO, PU/PD: 1.8V))A15: COM_AREA_01 (Antenna Ground)A16: COM_AREA_02 (LINK LED Channel 1 (O OD CMOS, 3.3V))A17: COM_AREA_03 (Antenna Ground)A18: COM_AREA_04 (SYNC Trigger Signal Channel 0 (O CMOS, 3.3V))A19: COM_AREA_05 (Antenna Ground)A20: COM_AREA_06 (Antenna Auxiliary Signal)A21: COM_AREA_07 (Antenna Ground)A22: UART_C_RX (Asynchronous serial data input port C (I CMOS, VCC_OUT_IO, PU/PD: 1.8V))A26: GND (Module Signal and power return and GND reference (P))A27: USB_D_SSTX_P (Transmit signal differential pairs for SuperSpeed on port D (O USB SS, USB SS, PU/PD: AC coupled off module))A28: USB_D_SSTX_N (Transmit signal differential pairs for SuperSpeed on port D (O USB SS, USB SS, PU/PD: AC coupled off module))A29: GND (Module Signal and power return and GND reference (P))A30: eDP_A_LANE0_P (Primary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module))A31: eDP_A_LANE0_N (Primary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module))A32: GND (Module Signal and power return and GND reference (P))A33: eDP_A_LANE2_P (Primary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module))A34: eDP_A_LANE2_N (Primary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module))B1: CSI_A_DATA0_P (CSI differential input (point to point) (I LVDS D-PHY / I LVDS M-PHY))B2: GND (Module Signal and power return and GND reference (P))B3: CSI_A_CLOCK_N (CSI differential clock input (point to point) (I LVDS D-PHY))B4: CSI_A_CLOCK_P (CSI differential clock input (point to point) (I LVDS D-PHY))B5: GND (Module Signal and power return and GND reference (P))B6: CSI_A_DATA3_N (CSI differential input (point to point) (I LVDS D-PHY / I LVDS M-PHY))B7: CSI_A_DATA3_P (CSI differential input (point to point) (I LVDS D-PHY / I LVDS M-PHY))B8: GND (Module Signal and power return and GND reference (P))B9: GND (Module Signal and power return and GND reference (P))B10: USB_C_SSRX_P (Receive signal differential pairs for SuperSpeed on port C (I USB SS, USB SS, PU/PD: AC coupled off module))B11: USB_C_SSRX_N (Receive signal differential pairs for SuperSpeed on port C (I USB SS, USB SS, PU/PD: AC coupled off module))B13: UART_A_TX (Asynchronous serial data output port A (O CMOS, VCC_OUT_IO, PU/PD: 1.8V))B15: COM_AREA_08 (Antenna Ground)B16: COM_AREA_09 (ACT LED Channel 1 (O OD CMOS, 3.3V))B17: COM_AREA_10 (Antenna Ground)B18: COM_AREA_11 (SYNC Trigger Signal Channel 1 (O CMOS, 3.3V))B19: COM_AREA_12 (Antenna Ground)B20: COM_AREA_13 (ACT LED Channel 0 (O OD CMOS, 3.3V))B21: COM_AREA_14 (Antenna Ground)B22: Vendor Defined (Defined by module manufacturer)B23: UART_C_TX (Asynchronous serial data output port C (O CMOS, VCC_OUT_IO, PU/PD: 1.8V))B25: USB_D_SSRX_P (Receive signal differential pairs for SuperSpeed on port D (I USB SS, USB SS, PU/PD: AC coupled off module))B26: USB_D_SSRX_N (Receive signal differential pairs for SuperSpeed on port D (I USB SS, USB SS, PU/PD: AC coupled off module))B27: GND (Module Signal and power return and GND reference (P))B28: GND (Module Signal and power return and GND reference (P))B29: VCC_8_TEST (Module power voltage testpoint (PO))B30: GND (Module Signal and power return and GND reference (P))B31: eDP_A_LANE1_P (Primary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module))B32: eDP_A_LANE1_N (Primary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module))B33: GND (Module Signal and power return and GND reference (P))B34: eDP_A_LANE3_P (Primary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module))B35: eDP_A_LANE3_N (Primary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module))C1: CSI_A_DATA0_N (CSI differential input (point to point) (I LVDS D-PHY/ I LVDS M-PHY))C2: CAM_MCK (Master clock output (O CMOS, 1.8V, PU/PD: shared with CAM_B))C3: CAM_A_SDA/ CSI_A_TX_N (I2C data for serial camera data support link or differential data lane (I/O OD CMOS / O LVDS M-PHY, 1.8V, PU/PD: PU 2.2K, MIPI-CSI 2.0 mode uses CAM_A_SDA MIPI-CSI 3.0 mode uses CSI_A_TX_N))C4: CAM_A_SCL/ CSI_A_TX_P (I2C clock for serial camera data support link or differential data lane (I/O OD CMOS / O LVDS M-PHY, 1.8V, PU/PD: PU 2.2K, MIPI-CSI 2.0 mode uses CAM_A_SCL MIPI-CSI 3.0 mode uses CSI_A_TX_P))C5: VCC_6_TEST (Module power voltage test point (PO))C6: ETH_B_MDC (Management bus clock signal for Ethernet B (O CMOS, 1.8V/2.5V/3.3V, PU/PD: Optional use))C7: ETH_B_MDIO (Management bus data signal for Ethernet B (I/O CMOS, 1.8V/2.5V/3.3V, PU/PD: Optional use))C8: USB_C_OC# (USB over-current for port C (I OD CMOS, 1.8V, PU/PD: PU 10k))C9: USB_C_VBUS (USB port 0 port power detection (I USB VBUS 5V, USB VBUS 5V))C10: USB_C_EN (Power enable for USB VBUS voltage (O CMOS, 1.8V))C11: GND (Module Signal and power return and GND reference (P))C13: UART_A_RTS ("Request to Send" handshake line for port A (O CMOS, VCC_OUT_IO, PU/PD: 1.8V))C14: UART_A_CTS ("Clear to Send" handshake line for port A (I CMOS, VCC_OUT_IO, PU/PD: 1.8V))C15: COM_AREA_15 (Main antenna test point)C16: Vendor Defined (Defined by module manufacturer)C17: COM_AREA_16 (Main antenna test point)C18: TEST_GENERIC (General purpose for testing (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V, The TEST_GENERIC function should be specified by module vendor.))C19: COM_AREA_17 (Auxiliary antenna test point)C20: SDIO_A_IOPWR (SDIO A Voltage. It is used to provide the IO Voltage Level (PO, 1.8V or 3.3V, PU/PD: Minimum current: 100mA))C21: COM_AREA_18 (Auxiliary antenna test point)C22: UART_D_RX (Asynchronous serial data input port D (I CMOS, VCC_OUT_IO, PU/PD: 1.8V))C23: UART_D_TX (Asynchronous serial data output port D (O CMOS, VCC_OUT_IO, PU/PD: 1.8V))C25: GND (Module Signal and power return and GND reference (P))C26: USB_D_EN (Power enable for USB VBUS voltage (O CMOS, 1.8V))C27: USB_D_VBUS (USB port 0 port power detection (I USB VBUS 5V, USB VBUS 5V))C28: USB_D_OC# (USB over-current for port D (I OD CMOS, 1.8V, PU/PD: PU 10k))C29: SPI_C_SDI (SPI C Serial Data Input (I CMOS, 1.8V))C30: SPI_C_CS0# (SPI C Master Chip Select 0 (O CMOS, 1.8V))C31: eDP_A_BL_PWM (Primary eDP panel brightness control through pulse width modulation (O CMOS, 1.8V))C32: GND (Module Signal and power return and GND reference (P))C33: eDP_A_AUX_P (Primary bidirectional eDP channel used for link management and device control (I/O LVDS DP, PD 100k, PU/PD: AC coupled off module))C34: eDP_A_AUX_N (Primary bidirectional eDP channel used for link management and device control (I/O LVDS DP, PD 100k, PU/PD: AC coupled off module))C35: GND (Module Signal and power return and GND reference (P))D1: GND (Module Signal and power return and GND reference (P))D2: ETH_B_(R)(G)MII_CRS (Carrier Sense port B (I CMOS, 1.8V/2.5V/3.3V))D3: GPIO_C_0 (General purpose I/O Contact C0 (I/O CMOS, 1.8V))D4: GPIO_C_1 (General purpose I/O Contact C1 (I/O CMOS, 1.8V))D5: GND (Module Signal and power return and GND reference (P))D6: Vendor Defined (Defined by module manufacturer)D7: Vendor Defined (Defined by module manufacturer)D8: GND (Module Signal and power return and GND reference (P))D9: USB_C_ID (Input Contact to announce OTG device insertion on USB 2.0 port (I OD CMOS, 1.8V, PU/PD: PU 10k))D10: USB_C_D_P (USB differential data pairs for port C (I/O USB, USB))D11: USB_C_D_N (USB differential data pairs for port C (I/O USB, USB))D13: UART_B_TX (Asynchronous serial data output port B (O CMOS, VCC_OUT_IO, PU/PD: 1.8V))D14: UART_B_RX (Asynchronous serial data input port B (I CMOS, VCC_OUT_IO, PU/PD: 1.8V))D15: UART_B_RTS ("Request to Send" handshake line for port B (O CMOS, VCC_OUT_IO, PU/PD: 1.8V))D16: UART_B_CTS ("Clear to Send" handshake line for port B (I CMOS, VCC_OUT_IO, PU/PD: 1.8V))D17: GPIO_A_0 (General purpose I/O Contact A0 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V))D18: GND (Module Signal and power return and GND reference (P))D19: GPIO_B_0 (General purpose I/O Contact B0 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V))D20: SDIO_A_WP (SDIO A Write Protect. This signal denotes the state of the write- protect tab on SD cards. (I OD CMOS, 1.8V or 3.3V, PU/PD: PU 10k, Tie to GND on carrier, if not used))D21: SDIO_A_PWR_EN (SDIO A Power Enable. This signal is used to enable the power being supplied to a SD/MMC card device. (O CMOS, 1.8V or 3.3V))D22: UART_CON_RX (Asynchronous serial data input port console (I CMOS, VCC_OUT_IO, PU/PD: 1.8V))D23: UART_CON_TX (Asynchronous serial data output port console (O CMOS, VCC_OUT_IO, PU/PD: 1.8V))D25: USB_D_D_P (USB differential data pairs for port D (I/O USB, USB))D26: USB_D_D_N (USB differential data pairs for port D (I/O USB, USB))D27: USB_D_ID (Input Contact to announce OTG device insertion on USB 2.0 port (I OD CMOS, 1.8V, PU/PD: PU 10k))D28: GND (Module Signal and power return and GND reference (P))D29: SPI_C_SCK (SPI C Serial Data Clock (O CMOS, 1.8V))D30: SPI_C_SDO (SPI C Serial Data Output (O CMOS, 1.8V))D31: eDP_A_BL_EN (Primary eDP panel backlight enable, active high (O CMOS, 1.8V))D32: eDP_A_AUX_SEL (Strapping signal to enable either HDMI or DP output (I CMOS, 1.8V, PU/PD: PD 1M, Pulled to GND on Carrier for DP operation in Dual Mode (DP++) implementations. Driven to 1.8V on carrier for HDMI mode Module must tolerate high level in stand-by mode))D33: eDP_A_HPD (Detection of Hot Plug / Unplug of primary eDP display and notification of the link layer. (I CMOS, 1.8V, PU/PD: PD 1M, Module must tolerate high level in stand-by mode))D34: GND (Module Signal and power return and GND reference (P))D35: eDP_B_LANE0_P (Secondary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module))E1: ETH_B_(R)(G)MII_COL (Collision detect (half speed only) port B (I CMOS, 1.8V/2.5V/3.3V))E2: GND (Module Signal and power return and GND reference (P))E3: GPIO_C_2/ CAM_B_PWR (Camera 1 Power Enable, active high output. (O CMOS, 1.8V))E4: GPIO_C_3/ CAM_B_RST# (Camera 1 reset, active low output (O CMOS, 1.8V))E15: GND (Module Signal and power return and GND reference (P))E16: ETH_A_(R)(G)MII_CRS (Carrier Sense port A (I CMOS, 1.8V/2.5V/3.3V))E17: GPIO_A_1 (General purpose I/O Contact A1 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V))E18: PWM_0/ DISP_BL_PWM (Primary Display brightness control through pulse width modulation (O CMOS, 1.8V))E19: GPIO_B_1 (General purpose I/O Contact B1 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V))E20: SDIO_A_CMD (SDIO A Command/Response. This signal is used for card initialization and for command transfers. During initialization mode this signal is open drain. During command transfer this signal is in push-pull mode. (I/O CMOS, 1.8V or 3.3V))E21: GND (Module Signal and power return and GND reference (P))E32: eDP_B_BL_EN (Secondary eDP panel backlight enable, active high (O CMOS, 1.8V))E33: eDP_B_BL_PWM (Secondary eDP panel brightness control through pulse width modulation (O CMOS, 1.8V))E34: eDP_B_LANE1_P (Secondary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module))E35: eDP_B_LANE0_N (Secondary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module))F1: ETH_B_(S)(R)(G)MII_TXD1 (Transmit data bit 1 port B (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _N when used as differential))F2: ETH_B_(S)(R)(G)MII_TXD3 (Transmit data bit 3 port B (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _N when used as differential))F3: GPIO_C_4/ DISP_VDD_EN (Primary Display power enable, active high (O CMOS, 1.8V))F4: GPIO_C_5/ DISP_BL_EN (Primary Display backlight enable, active high (O CMOS, 1.8V))F15: ETH_A_(R)(G)MII_COL (Collision detect (half speed only) port A (I CMOS, 1.8V/2.5V/3.3V))F16: GND (Module Signal and power return and GND reference (P))F17: GPIO_A_2 (General purpose I/O Contact A2 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V))F18: PWM_1 (Pulse width modulation 1 (O CMOS, VCC_OUT_IO, PU/PD: 1.8V))F19: GPIO_B_2 (General purpose I/O Contact B2 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V))F20: GND (Module Signal and power return and GND reference (P))F21: SDIO_A_CLK (SDIO A Clock. With each cycle of this signal a one-bit transfer on the command and each data line occurs. (O CMOS, 1.8V or 3.3V))F32: eDP_B_AUX_SEL (Auxilary Selection (I CMOS, 1.8V, PU/PD: PD 1M, Pulled to GND on Carrier for DP operation in Dual Mode (DP++) implementations. Driven to 1.8V on carrier for HDMI mode Module must tolerate high level in stand-by mode))F33: GND (Module Signal and power return and GND reference (P))F34: eDP_B_LANE1_N (Secondary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module))F35: GND (Module Signal and power return and GND reference (P))G1: ETH_B_(S)(R)(G)MII_TXD0 (Transmit data bit 0 (transmitted first) port B (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _P when used as differential))G2: ETH_B_(S)(R)(G)MII_TXD2 (Transmit data bit 2 port B (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _P when used as differential))G3: GPIO_C_6/ CAM_A_PWR (Camera Power Enable, active high output. (O CMOS, 1.8V))G4: GPIO_C_7/ CAM_A_RST# (Camera reset, active low output (O CMOS, 1.8V))G15: ETH_A_(S)(R)(G)MII_TXD1 (Transmit data bit 1 port A (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _N when used as differential))G16: ETH_A_(S)(R)(G)MII_TXD3 (Transmit data bit 3 port A (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _N when used as differential))G17: GPIO_A_3 (General purpose I/O Contact A3 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V))G18: PWM_2 (Pulse width modulation 2 (O CMOS, VCC_OUT_IO, PU/PD: 1.8V))G19: GPIO_B_3 (General purpose I/O Contact B3 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V))G20: SDIO_A_D0 (SDIO A Data lines. These signals operate in push-pull mode. (I/O CMOS, 1.8V or 3.3V))G21: SDIO_A_D1 (SDIO A Data lines. These signals operate in push-pull mode. (I/O CMOS, 1.8V or 3.3V))G32: eDP_B_HPD (Detection of Hot Plug / Unplug of secondary eDP display and notification of the link layer. (I CMOS, 1.8V, PU/PD: PD 1M, Module must tolerate high level in stand-by mode))G33: eDP_B_AUX_P (Secondary bidirectional eDP channel used for link management and device control (I/O LVDS DP, PD 100k, PU/PD: AC coupled off module))G34: GND (Module Signal and power return and GND reference (P))G35: eDP_B_LANE2_P (Secondary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module))H1: ETH_B_(R)(G)MII_TX_CLK (Transmit clock port B (I/O CMOS, 1.8V/2.5V/3.3V))H2: GND (Module Signal and power return and GND reference (P))H3: RGB_CS# (Chip select (O CMOS, 3.3V))H4: GND (Module Signal and power return and GND reference (P))H15: ETH_A_(S)(R)(G)MII_TXD0 (Transmit data bit 0 (transmitted first) port A (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _P when used as differential))H16: ETH_A_(S)(R)(G)MII_TXD2 (Transmit data bit 2 port A (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _P when used as differential))H17: GPIO_A_4 (General purpose I/O Contact A4 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V))H18: PWM_3 (Pulse width modulation 3 (O CMOS, VCC_OUT_IO, PU/PD: 1.8V))H19: GPIO_B_4 (General purpose I/O Contact B4 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V))H20: SDIO_A_D2 (SDIO A Data lines. These signals operate in push-pull mode. (I/O CMOS, 1.8V or 3.3V))H21: SDIO_A_D3 (SDIO A Data lines. These signals operate in push-pull mode. (I/O CMOS, 1.8V or 3.3V))H32: GND (Module Signal and power return and GND reference (P))H33: eDP_B_AUX_N (Secondary bidirectional eDP channel used for link management and device control (I/O LVDS DP, PD 100k, PU/PD: AC coupled off module))H34: eDP_B_LANE3_P (Secondary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module))H35: eDP_B_LANE2_N (Secondary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module))J1: ETH_B_(S)(R)(G)MII_RXD0 (Receive data bit 0 (received first) port B (I CMOS, 1.8V/2.5V/3.3V, PU/PD: _P when used as differential))J2: ETH_B_(R)(G)MII_TX_EN(_ER) (Transmit enable (Error) port B (O CMOS, 1.8V/2.5V/3.3V))J3: RGB_RESET# (Global Reset (O CMOS, 3.3V))J4: RGB_DE (Data Enable (O CMOS, 3.3V))J15: ETH_A_(R)(G)MII_TX_CLK (Transmit clock port A (I/O CMOS, 1.8V/2.5V/3.3V))J16: GND (Module Signal and power return and GND reference (P))J17: GPIO_A_5 (General purpose I/O Contact A5 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V))J18: PWM_4 (Pulse width modulation 4 (O CMOS, VCC_OUT_IO, PU/PD: 1.8V))J19: GPIO_B_5 (General purpose I/O Contact B5 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V))J20: GND (Module Signal and power return and GND reference (P))J21: SDIO_A_CD# (SDIO A Card Detect. This signal indicates when a SDIO/MMC card is present. (I OD CMOS, 1.8V or 3.3V, PU/PD: PU 10k))J32: CSI_B_CLOCK_N (CSI differential clock input (point to point) (I LVDS D-PHY))J33: GND (Module Signal and power return and GND reference (P))J34: eDP_B_LANE3_N (Secondary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module))J35: GND (Module Signal and power return and GND reference (P))K1: ETH_B_(S)(R)(G)MII_RXD1 (Receive data bit 1 port B (I CMOS, 1.8V/2.5V/3.3V, PU/PD: _N when used as differential))K2: ETH_B_(R)(G)MII_RX_ER (Receive error port B (I CMOS, 1.8V/2.5V/3.3V))K3: RGB_HSYNC (horizontal synch (O CMOS, 3.3V))K4: RGB_DISP (Display ON/OFF (O CMOS, 3.3V))K15: ETH_A_(S)(R)(G)MII_RXD0 (Receive data bit 0 (received first) port A (I CMOS, 1.8V/2.5V/3.3V, PU/PD: _P when used as differential))K16: ETH_A_(R)(G)MII_TX_EN(_ER) (Transmit enable (Error) port A (O CMOS, 1.8V/2.5V/3.3V))K17: GPIO_A_6/ SPI_A_CS1# (General purpose I/O Contact A6 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V, Dual function: SPI_A_CS1#))K18: PWM_5 (Pulse width modulation 5 (O CMOS, VCC_OUT_IO, PU/PD: 1.8V))K19: GPIO_B_6 (General purpose I/O Contact B6 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V))K20: SDIO_B_CLK (SDIO B Clock. With each cycle of this signal a one-bit transfer on the command and each data line occurs. (O CMOS, 1.8V or 3.3V))K21: SDIO_B_CMD (SDIO B Command/Response. This signal is used for card initialization and for command transfers. During initialization mode (I/O CMOS, 1.8V or 3.3V))K32: GND (Module Signal and power return and GND reference (P))K33: CSI_B_CLOCK_P (CSI differential clock input (point to point) (I LVDS D-PHY))K34: GND (Module Signal and power return and GND reference (P))K35: PCIe_B_HSO0_P (Differential PCIe link B transmit data pair (O LVDS PCIE, AC coupled off module))L1: ETH_B_(R)(G)MII_RX_DV(_ER) (Receive data valid (Error) port B (I CMOS, 1.8V/2.5V/3.3V))L2: GND (Module Signal and power return and GND reference (P))L3: RGB_VSYNC (Vertical synch (O CMOS, 3.3V))L4: GND (Module Signal and power return and GND reference (P))L15: ETH_A_(S)(R)(G)MII_RXD1 (Receive data bit 1 port A (I CMOS, 1.8V/2.5V/3.3V, PU/PD: _N when used as differential))L16: ETH_A_(R)(G)MII_RX_ER (Receive error port A (I CMOS, 1.8V/2.5V/3.3V))L17: GPIO_A_7/ SPI_B_CS1# (General purpose I/O Contact A7 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V, Dual function: SPI_B_CS1#))L18: GND (Module Signal and power return and GND reference (P))L19: GPIO_B_7 (General purpose I/O Contact B7 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V))L20: SDIO_B_D0 (SDIO B Data lines. These signals operate in push-pull mode. (I/O CMOS, 1.8V or 3.3V))L21: SDIO_B_D1 (SDIO B Data lines. These signals operate in push-pull mode. (I/O CMOS, 1.8V or 3.3V))L32: CSI_B_DATA0_N (CSI differential input (point to point) (I LVDS D-PHY/ I LVDS M-PHY))L33: PCIe_B_PERST# (PCIe Port B reset output (O CMOS, 1.8V))L34: PCIe_B_HSI0_P (Differential PCIe link B receive data pair (I LVDS PCIE, AC coupled off module))L35: PCIe_B_HSO0_N (Differential PCIe link B transmit data pair (O LVDS PCIE, AC coupled off module))M1: ETH_B_(R)(G)MII_RXD2 (Receive data bit 2 port B (I CMOS, 1.8V/2.5V/3.3V))M2: ETH_B_SDP (Ethernet port B System Defined Contact (I/O CMOS, 1.8V/2.5V/3.3V))M3: RGB_B5 (Blue data bit 5 (O CMOS, 3.3V))M4: RGB_(PIXEL)CLK (Pixel clock signal (O CMOS, 3.3V))M15: ETH_A_(R)(G)MII_RX_DV(_ER) (Receive data valid port A (I CMOS, 1.8V/2.5V/3.3V))M16: GND (Module Signal and power return and GND reference (P))M17: ETH_IOPWR (ETH voltage. It is used to provide the IO Voltage Level for all Ethernet interfaces. (PO, 1.8V/2.5V/3.3V, PU/PD: Minimum current: 100mA))M18: ADC_0 (Analog Digital Converter 0 (Analog, 0V – 1.8V))M19: VCC_2_TEST (Module power voltage testpoint (PO))M20: GND (Module Signal and power return and GND reference (P))M21: SDIO_B_D2 (SDIO B Data lines. These signals operate in push-pull mode. (I/O CMOS, 1.8V or 3.3V))M32: GND (Module Signal and power return and GND reference (P))M33: CSI_B_DATA0_P (CSI differential input (point to point) (I LVDS D-PHY / I LVDS M-PHY))M34: PCIe_B_HSI0_N (Differential PCIe link B receive data pair (I LVDS PCIE, AC coupled off module))M35: GND (Module Signal and power return and GND reference (P))N1: ETH_B_(R)(G)MII_RXD3 (Receive data bit 3 port B (I CMOS, 1.8V/2.5V/3.3V))N2: RESERVED (Reserved for future use (NC))N3: RGB_B3 (Blue data bit 3 (O CMOS, 3.3V))N4: RGB_B4 (Blue data bit 4 (O CMOS, 3.3V))N15: ETH_A_(R)(G)MII_RXD2 (Receive data bit 2 port A (I CMOS, 1.8V/2.5V/3.3V))N16: ETH_A_SDP (Ethernet port A System Defined Contact (I/O CMOS, 1.8V/2.5V/3.3V))N17: JTAG_TCK(SWCLK) (Test Clock (I CMOS, VCC_OUT_IO, PU/PD: 1.8V))N18: ADC_1 (Analog Digital Converter 1 (Analog, 0V – 1.8V))N19: JTAG_TMS(SWDIO) (Test Mode Select (I CMOS, VCC_OUT_IO, PU/PD: 1.8V))N20: SDIO_B_D3 (SDIO B Data lines. These signals operate in push-pull mode. (I/O CMOS, 1.8V or 3.3V))N21: SDIO_B_D4 (SDIO B Data lines. These signals operate in push-pull mode. (I/O CMOS, 1.8V or 3.3V))N32: CSI_B_DATA1_N (CSI differential input (point to point) (I LVDS D-PHY / I LVDS M-PHY))N33: ETH_CDE_MDC (Management bus clock signal for Ethernet C/D/E (O CMOS, 1.8V/2.5V/3.3V, PU/PD: Optional use))N34: GND (Module Signal and power return and GND reference (P))N35: ETH_C_(R)(G)MII_TX_CLK (Transmit clock port C (I/O CMOS, 1.8V/2.5V/3.3V))P1: ETH_B_(R)(G)MII_RX_CLK (Receive clock port B (I/O CMOS, 1.8V/2.5V/3.3V))P2: GND (Module Signal and power return and GND reference (P))P3: RGB_B2 (Blue data bit 2 (O CMOS, 3.3V))P4: GND (Module Signal and power return and GND reference (P))P15: ETH_A_(R)(G)MII_RXD3 (Receive data bit 3 port A (I CMOS, 1.8V/2.5V/3.3V))P16: Vendor Defined (Defined by module manufacturer)P17: JTAG_TDI (Test Data Input (I CMOS, VCC_OUT_IO, PU/PD: 1.8V))P18: GND (Module Signal and power return and GND reference (P))P19: JTAG_RTCK (Returned Test Clock (O CMOS, VCC_OUT_IO, PU/PD: 1.8V))P20: SDIO_B_D5 (SDIO B Data lines. These signals operate in push-pull mode. (I/O CMOS, 1.8V or 3.3V))P21: SDIO_B_D6 (SDIO B Data lines. These signals operate in push-pull mode. (I/O CMOS, 1.8V or 3.3V))P32: CSI_B_DATA1_P (CSI differential input (point to point) (I LVDS D-PHY / I LVDS M-PHY))P33: ETH_CDE_MDIO (Management bus data signal for Ethernet C/D/E (I/O CMOS, 1.8V/2.5V/3.3V, PU/PD: Optional use))P34: CSI_B_DATA2_N (CSI differential input (point to point) (I LVDS D-PHY / I LVDS M-PHY))P35: ETH_C_(R)(G)MII_RXD3 (Receive data bit 3 port C (I CMOS, 1.8V/2.5V/3.3V))R1: GND (Module Signal and power return and GND reference (P))R2: PCIe_SM_ALERT# (SMBus Alert# (interrupt) signal (I OD CMOS, 1.8V, PU/PD: PU 2k2))R3: RGB_B1 (Blue data bit 1 (O CMOS, 3.3V))R4: RGB_B0 (Blue data bit 0 (O CMOS, 3.3V))R15: ETH_A_(R)(G)MII_RX_CLK (Receive clock port A (I/O CMOS, 1.8V/2.5V/3.3V))R16: GND (Module Signal and power return and GND reference (P))R17: JTAG_TDO(SWO) (Test Data Output (O CMOS, VCC_OUT_IO, PU/PD: 1.8V))R18: BOOT_SEL1# (I OD CMOS (1.8V, PU 10k, PU/PD: The boot medium is the choice of the module vendor.))R19: JTAG_nTRST (Test Reset, Active Low (I CMOS, VCC_OUT_IO, PU/PD: 1.8V))R20: GND (Module Signal and power return and GND reference (P))R21: SDIO_B_D7 (SDIO B Data lines. These signals operate in push-pull mode. (I/O CMOS, 1.8V or 3.3V))R32: GND (Module Signal and power return and GND reference (P))R33: CSI_B_DATA2_P (CSI differential input (point to point) (I LVDS D-PHY / I LVDS M-PHY))R34: ETH_C_SDP (Ethernet port C System Defined Contact (I/O CMOS, 1.8V/2.5V/3.3V))R35: ETH_C_(R)(G)MII_RXD2 (Receive data bit 2 port C (I CMOS, 1.8V/2.5V/3.3V))T1: PCIe_SMCLK (System management I2C bus CLK (O OD CMOS, 1.8V, PU/PD: PU 2k2))T2: PCIe_WAKE# (PCIe wake up interrupt to host – common to PCIe links A, B, C, D (I OD CMOS, 1.8V, PU/PD: PU 10k))T3: RGB_G4 (Green data bit 4 (O CMOS, 3.3V))T4: RGB_G5 (Green data bit 5 (O CMOS, 3.3V))T15: ETH_MDIO (Management bus data signal for Ethernet (I/O CMOS, 1.8V/2.5V/3.3V, PU/PD: Can be used for all ETH ports or for A exclusively))T16: ETH_MDC (Management bus clock signal for Ethernet (O CMOS, 1.8V/2.5V/3.3V, PU/PD: Can be used for all ETH ports or for A exclusively))T17: FORCE_RECOVERY# (If low on carrier board module enters recovery mode. (I OD CMOS, 1.8V, PU/PD: PU 10k, The recovery mode should be specified by module vendor.))T18: I2S_B_LRCLK (I2S Left & Right synchronization clock (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V, Module Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode))T19: I2S_B_BITCLK (I2S Digital audio clock (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V, Module Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode))T20: SDIO_B_IOPWR (SDIO B Voltage. It is used to provide the IO Voltage Level (PO, 1.8V or 3.3V, PU/PD: Minimum current: 100mA))T21: SDIO_B_CD# (SDIO B Card Detect. This signal indicates when a SDIO/MMC card is present. (I OD CMOS, 1.8V or 3.3V, PU/PD: PU 10k))T32: CSI_B_DATA3_N (CSI differential input (point to point) (I LVDS D-PHY / I LVDS M-PHY))T33: CSI_B_DATA3_P (CSI differential input (point to point) (I LVDS D-PHY / I LVDS M-PHY))T34: GND (Module Signal and power return and GND reference (P))T35: ETH_C_(R)(G)MII_RX_DV(_ER) (Receive data valid (Error) port C (I CMOS, 1.8V/2.5V/3.3V))U1: PCIe_SMDAT (System management I2C bus DATA (I/O OD CMOS, 1.8V, PU/PD: PU 2k2))U2: GND (Module Signal and power return and GND reference (P))U3: RGB_G3 (Green data bit 3 (O CMOS, 3.3V))U4: GND (Module Signal and power return and GND reference (P))U15: SPI_A_SDI_(IO1) (SPI_A_SDI_(IO1))U16: SPI_A_SCK (SPI A Serial Data Clock (O CMOS, VCC_OUT_IO, PU/PD: 1.8V))U17: RESET_IN# (Reset input from Carrier board. Carrier drives low to force a Module reset, floats the line otherwise. (I OD CMOS, 1.8V, PU/PD: PU 10K))U18: VCC_OUT_IO (Provides IO voltage level for several interfaces to connect (PO, 1.8V/3.3V, PU/PD: 1.8V/3.3V on size 0, 1.8V on all other sizes – minimum current: 100 mA))U19: BOOT_SEL0# (I OD CMOS (1.8V, PU 10k, PU/PD: The boot medium is the choice of the module vendor.))U20: SDIO_B_WP (SDIO B Write Protect. This signal denotes the state of the write- protect tab on SD cards. (I OD CMOS, 1.8V or 3.3V, PU/PD: PU 10k, Tie to GND on carrier, if not used))U21: SDIO_B_PWR_EN (SDIO B Power Enable. This signal is used to enable the power being supplied to a SD/MMC card device. (O CMOS, 1.8V or 3.3V))U32: GPIO_D_0 (General purpose I/O Contact D0 (I/O CMOS, 1.8V))U33: GPIO_D_1 (General purpose I/O Contact D1 (I/O CMOS, 1.8V))U34: ETH_C_(R)(G)MII_RX_ER (Receive error port C (I CMOS, 1.8V/2.5V/3.3V))U35: ETH_C_(S)(R)(G)MII_RXD1 (Receive data bit 1 port C (I CMOS, 1.8V/2.5V/3.3V, PU/PD: _N when used as differential))V1: GND (Module Signal and power return and GND reference (P))V2: PCIe_A_PERST# (PCIe Port A reset output (O CMOS, 1.8V))V3: RGB_G1 (Green data bit 1 (O CMOS, 3.3V))V4: RGB_G2 (Green data bit 2 (O CMOS, 3.3V))V15: SPI_A_SDO_(IO0) (SPI_A_SDO_(IO0))V16: GND (Module Signal and power return and GND reference (P))V17: CARRIER_PWR_EN (Carrier board circuits should not be powered up until the module asserts the CARRIER_PWR_EN signal (O CMOS, 1.8V))V18: I2S_MCLK (Master clock output to I2S codec(s) (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V))V19: I2S_B_DATA_IN (I2S B Digital audio Input (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V))V20: GND (Module Signal and power return and GND reference (P))V21: I2S_A_DATA_IN (I2S A Digital audio Input (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V))V32: GPIO_D_2 (General purpose I/O Contact D2 (I/O CMOS, 1.8V))V33: GPIO_D_3 (General purpose I/O Contact D3 (I/O CMOS, 1.8V))V34: ETH_C_(R)(G)MII_TX_EN(_ER) (Transmit enable (Error) port C (O CMOS, 1.8V/2.5V/3.3V))V35: ETH_C_(S)(R)(G)MII_RXD0 (Receive data bit 0 (received first) port C (I CMOS, 1.8V/2.5V/3.3V, PU/PD: _P when used as differential))W1: PCIe_REFCLK_P (Differential PCIe reference clock output (O LVDS PCIE))W2: PCIe_CLKREQ# (PCIe reference clock request (I OD CMOS, 1.8V, PU/PD: PU 10k))W3: GND (Module Signal and power return and GND reference (P))W4: RGB_G0 (Green data bit 0 (O CMOS, 3.3V))W15: SPI_A_HOLD_(IO3) (SPI_A_HOLD_(IO3))W16: SPI_A_WP_(IO2) (SPI_A_WP_(IO2))W17: RTC_PWR (Low current RTC circuit backup power – 3.0V nominal. May be sourced from a Carrier based Lithium cell or Super Cap. (P, If RTC is implemented, Module Vendor should ensure proper function of RTC during active main supply if this pin is not used))W18: I2S_A_LRCLK (I2S Left & Right synchronization clock (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V, Module Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode))W19: I2S_B_DATA_OUT (I2S B Digital audio Output (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V))W20: I2S_A_BITCLK (I2S Digital audio clock (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V, Module Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode))W21: I2S_A_DATA_OUT (I2S A Digital audio Output (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V))W32: GPIO_D_4 (General purpose I/O Contact D4 (I/O CMOS, 1.8V))W33: GPIO_D_5 (General purpose I/O Contact D5 (I/O CMOS, 1.8V))W34: GND (Module Signal and power return and GND reference (P))W35: ETH_C_(R)(G)MII_RX_CLK (Receive clock port C (I/O CMOS, 1.8V/2.5V/3.3V))Y1: PCIe_REFCLK_N (Differential PCIe reference clock output (O LVDS PCIE))Y2: GND (Module Signal and power return and GND reference (P))Y3: VCC_5_TEST (Module power voltage test point (PO))Y4: RGB_R5 (Red data bit 5 (O CMOS, 3.3V))Y5: RGB_R4 (Red data bit 4 (O CMOS, 3.3V))Y6: RGB_R2 (Red data bit 2 (O CMOS, 3.3V))Y7: RGB_R0 (Red data bit 0 (O CMOS, 3.3V))Y8: VCC_IN_5V (Module power input voltage of 5V (P, Tolerance: 5V +-5%))Y9: VCC_IN_5V (Module power input voltage of 5V (P, Tolerance: 5V +-5%))Y10: VCC_IN_5V (Module power input voltage of 5V (P, Tolerance: 5V +-5%))Y11: VCC_IN_5V (Module power input voltage of 5V (P, Tolerance: 5V +-5%))Y13: CARRIER_STBY# (The Module shall drive this signal low when the system is in a standby power state (O CMOS, 1.8V, PU/PD: Optional))Y14: RESET_OUT# (Reset output from CPU to reset peripherals on Carrier. (O CMOS, 1.8V))Y15: SPI_A_CS0# (SPI A Master Chip Select 0 (O CMOS, VCC_OUT_IO, PU/PD: 1.8V))Y16: VCC_3_TEST (Module power voltage testpoint (PO))Y17: VCC_IN_5V (Module power input voltage of 5V – Primary voltage rail for size S, M and L modules (P, Tolerance: 5V +-5%))Y18: GND (Module Signal and power return and GND reference (P))Y19: VCC_IN_3V3 (Module power input voltage of 3.3V – Primary voltage rail for 0 size modules (P, Tolerance: 3.3V +- 5%))Y20: VCC_4_TEST (Module power voltage testpoint (PO))Y21: SPI_B_SCK (SPI B Serial Data Clock (O CMOS, VCC_OUT_IO, PU/PD: 1.8V))Y22: SPI_B_SDI (SPI B Serial Data Input (I CMOS, VCC_OUT_IO, PU/PD: 1.8V))Y23: SPI_B_SDO (SPI B Serial Data Output (O CMOS, VCC_OUT_IO, PU/PD: 1.8V))Y25: VCC_IN_5V (Module power input voltage of 5V (P, Tolerance: 5V +-5%))Y26: VCC_IN_5V (Module power input voltage of 5V (P, Tolerance: 5V +-5%))Y27: VCC_IN_5V (Module power input voltage of 5V (P, Tolerance: 5V +-5%))Y28: VCC_IN_5V (Module power input voltage of 5V (P, Tolerance: 5V +-5%))Y29: Vendor Defined (Defined by module manufacturer)Y30: Vendor Defined (Defined by module manufacturer)Y31: Vendor Defined (Defined by module manufacturer)Y32: GPIO_D_6 (General purpose I/O Contact D6 (I/O CMOS, 1.8V))Y33: GPIO_D_7/ SPI_C_CS1# (General purpose I/O Contact D7 (I/O CMOS, 1.8V, PU/PD: Dual function: SPI_C_CS1#))Y34: ETH_C_(S)(R)(G)MII_TXD2 (Transmit data bit 2 port C (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _P when used as differential))Y35: ETH_C_(S)(R)(G)MII_TXD0 (Transmit data bit 0 (transmitted first) port C (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _P when used as differential))AA1: GND (Module Signal and power return and GND reference (P))AA2: RESERVED (Reserved for future use (NC))AA3: DSI_TE (DSI panel tearing effect signal (I CMOS, 1.8V, PU/PD: not used in LVDS mode))AA4: GND (Module Signal and power return and GND reference (P))AA5: RGB_R3 (Red data bit 3 (O CMOS, 3.3V))AA6: RGB_R1 (Red data bit 1 (O CMOS, 3.3V))AA7: GND (Module Signal and power return and GND reference (P))AA8: GND (Module Signal and power return and GND reference (P))AA9: PWR_BTN# (Power-button input from Carrier board. Carrier to float the line in in-active state. Active low, level sensitive. Should be de-bounced on the Module. (I OD CMOS, 1.8 to 5V, PU/PD: PU 10K))AA10: GND (Module Signal and power return and GND reference (P))AA11: GND (Module Signal and power return and GND reference (P))AA13: RESERVED (Reserved for future use (NC))AA14: GND (Module Signal and power return and GND reference (P))AA15: I2C_A_SCL (I2C Port A Clock Signal (I/O OD CMOS, VCC_OUT_IO, PU/PD: 1.8V, PU 2k2))AA16: I2C_A_SDA (I2C Port A Data Signal (I/O OD CMOS, VCC_OUT_IO, PU/PD: 1.8V, PU 2k2))AA17: GND (Module Signal and power return and GND reference (P))AA18: V_BAT (Module power input battery voltage (P))AA19: GND (Module Signal and power return and GND reference (P))AA20: I2C_B_SCL (I2C Port B Clock Signal (I/O OD CMOS, VCC_OUT_IO, PU/PD: 1.8V, PU 2k2))AA21: I2C_B_SDA (I2C Port B Data Signal (I/O OD CMOS, VCC_OUT_IO, PU/PD: 1.8V, PU 2k2))AA22: GND (Module Signal and power return and GND reference (P))AA23: SPI_B_CS0# (SPI B Master Chip Select 0 (O CMOS, VCC_OUT_IO, PU/PD: 1.8V))AA25: GND (Module Signal and power return and GND reference (P))AA26: GND (Module Signal and power return and GND reference (P))AA27: GND (Module Signal and power return and GND reference (P))AA28: GND (Module Signal and power return and GND reference (P))AA29: Vendor Defined (Defined by module manufacturer)AA30: Vendor Defined (Defined by module manufacturer)AA31: Vendor Defined (Defined by module manufacturer)AA32: GND (Module Signal and power return and GND reference (P))AA33: VCC_7_TEST (Module power voltage testpoint (PO))AA34: ETH_C_(S)(R)(G)MII_TXD3 (Transmit data bit 3 port C (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _N when used as differential))AA35: ETH_C_(S)(R)(G)MII_TXD1 (Transmit data bit 1 port C (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _N when used as differential))AB1: PCIe_A_HSI0_P (Differential PCIe link A receive data pair (I LVDS PCIE, AC coupled off module))AB2: PCIe_A_HSI0_N (Differential PCIe link A receive data pair (I LVDS PCIE, AC coupled off module))AB3: GND (Module Signal and power return and GND reference (P))AB4: DSI_DATA3_P/ LVDS_A_LANE3_P (DSI differential output (point to point) / LVDS channel A differential pair data lines (O LVDS D-PHY / O LVDS LCD, Alternate use: LVDS_A_ LANE3_P))AB5: DSI_DATA3_N/ LVDS_A_LANE3_N (DSI differential output (point to point) / LVDS channel A differential pair data lines (O LVDS D-PHY / O LVDS LCD, Alternate use: LVDS_A_ LANE3_N))AB6: GND (Module Signal and power return and GND reference (P))AB7: DSI_CLOCK_P/ LVDS_A_CLK_P (DSI differential clock output (point to point) / LVDS channel A differential pair clock lines (O LVDS D-PHY / O LVDS LCD, Alternate use: LVDS_A_CLK_P))AB8: DSI_CLOCK_N/ LVDS_A_CLK_N (DSI differential clock output (point to point) / LVDS channel A differential pair clock lines (O LVDS D-PHY / O LVDS LCD, Alternate use: LVDS_A_CLK_N))AB9: GND (Module Signal and power return and GND reference (P))AB10: DSI_DATA0_P/ LVDS_A_LANE0_P (DSI differential output (point to point) / LVDS channel A differential pair data lines (O LVDS D-PHY / O LVDS LCD, Alternate use: LVDS_A_LANE0_P))AB11: DSI_DATA0_N/ LVDS_A_LANE0_N (DSI differential output (point to point) / LVDS channel A differential pair data lines (O LVDS D-PHY / O LVDS LCD, Alternate use: LVDS_A_LANE0_N))AB13: USB_A_D_N (USB differential data pairs for port A (I/O USB, USB))AB14: USB_A_ID (Input Contact to announce OTG device insertion on USB 2.0 port (I OD CMOS, 1.8V, PU/PD: PU 10k))AB15: GND (Module Signal and power return and GND reference (P))AB16: USB_A_VBUS (USB port 0 port power detection (I USB VBUS 5V, USB VBUS 5V))AB17: CAN_A_RX (CAN port A Receive input (I CMOS, VCC_OUT_IO, PU/PD: 1.8V))AB18: V_BAT (Module power input battery voltage (P))AB19: CAN_B_RX (CAN port B Receive input (I CMOS, VCC_OUT_IO, PU/PD: 1.8V))AB20: USB_B_VBUS (USB port 0 port power detection (I USB VBUS 5V, USB VBUS 5V))AB21: GND (Module Signal and power return and GND reference (P))AB22: USB_B_ID (Input Contact to announce OTG device insertion on USB 2.0 port (I OD CMOS, 1.8V, PU/PD: PU 10k))AB23: USB_B_D_N (USB differential data pairs for port B (I/O USB, USB))AB25: CAM_B_SCL/ CSI_B_TX_P (I2C clock for serial camera data support link or differential data lane (I/O OD CMOS / O LVDS M-PHY, 1.8V, PU/PD: PU 2.2K, MIPI-CSI 2.0 mode uses CAM_B_SCL MIPI-CSI 3.0 mode uses CSI_B_TX_P))AB26: CAM_B_SDA/ CSI_B_TX_N (I2C data for serial camera data support link or differential data lane (I/O OD CMOS / O LVDS M-PHY, 1.8V, PU/PD: PU 2.2K, MIPI-CSI 2.0 mode uses CAM_B_SDA MIPI-CSI 3.0 mode uses CSI_B_TX_N))AB27: UFS_RESET# (UFS reset output (O CMOS, 1.8V / 1.2V, PU/PD: USF 3.0 need 1.2V I/O level))AB28: GND (Module Signal and power return and GND reference (P))AB29: UFS_TX1_P (UFS differential output (point to point) (O LVDS UFS))AB30: UFS_TX1_N (UFS differential output (point to point) (O LVDS UFS))AB31: GND (Module Signal and power return and GND reference (P))AB32: UFS_RX1_P (UFS differential input (point to point) (I LVDS UFS))AB33: UFS_RX1_N (UFS differential input (point to point) (I LVDS UFS))AB34: GND (Module Signal and power return and GND reference (P))AB35: ETH_C_(R)(G)MII_COL (Collision detect (half speed only) port C (I CMOS, 1.8V/2.5V/3.3V))AC2: PCIe_A_HSO0_P (Differential PCIe link A transmit data pair (O LVDS PCIE, AC coupled off module))AC3: PCIe_A_HSO0_N (Differential PCIe link A transmit data pair (O LVDS PCIE, AC coupled off module))AC4: GND (Module Signal and power return and GND reference (P))AC5: DSI_DATA2_P/ LVDS_A_LANE2_P (DSI differential output (point to point) / LVDS channel A differential pair data lines (O LVDS D-PHY / O LVDS LCD, Alternate use: LVDS_A_ LANE2_P))AC6: DSI_DATA2_N/ LVDS_A_LANE2_N (DSI differential output (point to point) / LVDS channel A differential pair data lines (O LVDS D-PHY / O LVDS LCD, Alternate use: LVDS_A_ LANE2_N))AC7: GND (Module Signal and power return and GND reference (P))AC8: DSI_DATA1_P/ LVDS_A_LANE1_P (DSI differential output (point to point) / LVDS channel A differential pair data lines (O LVDS D-PHY / O LVDS LCD, Alternate use: LVDS_A_ LANE1_P))AC9: DSI_DATA1_N/ LVDS_A_LANE1_N (DSI differential output (point to point) / LVDS channel A differential pair data lines (O LVDS D-PHY / O LVDS LCD, Alternate use: LVDS_A_ LANE1_N))AC10: GND (Module Signal and power return and GND reference (P))AC14: USB_A_D_P (USB differential data pairs for port A (I/O USB, USB))AC15: USB_A_OC# (USB over-current for port A (I OD CMOS, 1.8V, PU/PD: PU 10k))AC16: USB_A_EN (Power enable for USB VBUS voltage (O CMOS, 1.8V))AC17: CAN_A_TX (CAN port A Transmit output (O CMOS, VCC_OUT_IO, PU/PD: 1.8V))AC18: DEBUG_EN (Enables JTAG function (I CMOS, VCC_OUT_IO, PU/PD: 1.8V))AC19: CAN_B_TX (CAN port B Transmit output (O CMOS, VCC_OUT_IO, PU/PD: 1.8V))AC20: USB_B_EN (Power enable for USB VBUS voltage (O CMOS, 1.8V))AC21: USB_B_OC# (USB over-current for port B (I OD CMOS, 1.8V, PU/PD: PU 10k))AC22: USB_B_D_P (USB differential data pairs for port B (I/O USB, USB))AC26: UFS_CLK (UFS reference clock output (O CMOS, 1.8V / 1.2 V, PU/PD: USF 3.0 need 1.2V I/O level))AC27: GND (Module Signal and power return and GND reference (P))AC28: UFS_TX0_P (UFS differential output (point to point) (O LVDS UFS))AC29: UFS_TX0_N (UFS differential output (point to point) (O LVDS UFS))AC30: GND (Module Signal and power return and GND reference (P))AC31: UFS_RX0_P (UFS differential input (point to point) (I LVDS UFS))AC32: UFS_RX0_N (UFS differential input (point to point) (I LVDS UFS))AC33: GND (Module Signal and power return and GND reference (P))AC34: ETH_C_(R)(G)MII_CRS (Carrier Sense port C (I CMOS, 1.8V/2.5V/3.3V))pinoutdb.org
Pin-Tabelle476
PinSignal / NameTypAlternative Funktionen
A2CSI_A_DATA1_NDigital
CSI differential input (point to point) (I LVDS D-PHY / I LVDS M-PHY)
A3CSI_A_DATA1_PDigital
CSI differential input (point to point) (I LVDS D-PHY / I LVDS M-PHY)
A4GNDGround
Module Signal and power return and GND reference (P)
A5CSI_A_DATA2_NDigital
CSI differential input (point to point) (I LVDS D-PHY / I LVDS M-PHY)
A6CSI_A_DATA2_PDigital
CSI differential input (point to point) (I LVDS D-PHY / I LVDS M-PHY)
A7GNDGround
Module Signal and power return and GND reference (P)
A8USB_C_SSTX_PDigital
Transmit signal differential pairs for SuperSpeed on port C (O USB SS, USB SS, PU/PD: AC coupled off module)
A9USB_C_SSTX_NDigital
Transmit signal differential pairs for SuperSpeed on port C (O USB SS, USB SS, PU/PD: AC coupled off module)
A10GNDGround
Module Signal and power return and GND reference (P)
A14UART_A_RXDigital
Asynchronous serial data input port A (I CMOS, VCC_OUT_IO, PU/PD: 1.8V)
A15COM_AREA_01Digital
Antenna Ground
A16COM_AREA_02Digital
LINK LED Channel 1 (O OD CMOS, 3.3V)
A17COM_AREA_03Digital
Antenna Ground
A18COM_AREA_04Digital
SYNC Trigger Signal Channel 0 (O CMOS, 3.3V)
A19COM_AREA_05Digital
Antenna Ground
A20COM_AREA_06Digital
Antenna Auxiliary Signal
A21COM_AREA_07Digital
Antenna Ground
A22UART_C_RXDigital
Asynchronous serial data input port C (I CMOS, VCC_OUT_IO, PU/PD: 1.8V)
A26GNDGround
Module Signal and power return and GND reference (P)
A27USB_D_SSTX_PDigital
Transmit signal differential pairs for SuperSpeed on port D (O USB SS, USB SS, PU/PD: AC coupled off module)
A28USB_D_SSTX_NDigital
Transmit signal differential pairs for SuperSpeed on port D (O USB SS, USB SS, PU/PD: AC coupled off module)
A29GNDGround
Module Signal and power return and GND reference (P)
A30eDP_A_LANE0_PDigital
Primary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module)
A31eDP_A_LANE0_NDigital
Primary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module)
A32GNDGround
Module Signal and power return and GND reference (P)
A33eDP_A_LANE2_PDigital
Primary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module)
A34eDP_A_LANE2_NDigital
Primary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module)
B1CSI_A_DATA0_PDigital
CSI differential input (point to point) (I LVDS D-PHY / I LVDS M-PHY)
B2GNDGround
Module Signal and power return and GND reference (P)
B3CSI_A_CLOCK_NDigital
CSI differential clock input (point to point) (I LVDS D-PHY)
B4CSI_A_CLOCK_PDigital
CSI differential clock input (point to point) (I LVDS D-PHY)
B5GNDGround
Module Signal and power return and GND reference (P)
B6CSI_A_DATA3_NDigital
CSI differential input (point to point) (I LVDS D-PHY / I LVDS M-PHY)
B7CSI_A_DATA3_PDigital
CSI differential input (point to point) (I LVDS D-PHY / I LVDS M-PHY)
B8GNDGround
Module Signal and power return and GND reference (P)
B9GNDGround
Module Signal and power return and GND reference (P)
B10USB_C_SSRX_PDigital
Receive signal differential pairs for SuperSpeed on port C (I USB SS, USB SS, PU/PD: AC coupled off module)
B11USB_C_SSRX_NDigital
Receive signal differential pairs for SuperSpeed on port C (I USB SS, USB SS, PU/PD: AC coupled off module)
B13UART_A_TXDigital
Asynchronous serial data output port A (O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
B15COM_AREA_08Digital
Antenna Ground
B16COM_AREA_09Digital
ACT LED Channel 1 (O OD CMOS, 3.3V)
B17COM_AREA_10Digital
Antenna Ground
B18COM_AREA_11Digital
SYNC Trigger Signal Channel 1 (O CMOS, 3.3V)
B19COM_AREA_12Digital
Antenna Ground
B20COM_AREA_13Digital
ACT LED Channel 0 (O OD CMOS, 3.3V)
B21COM_AREA_14Digital
Antenna Ground
B22Vendor DefinedDigital
Defined by module manufacturer
B23UART_C_TXDigital
Asynchronous serial data output port C (O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
B25USB_D_SSRX_PDigital
Receive signal differential pairs for SuperSpeed on port D (I USB SS, USB SS, PU/PD: AC coupled off module)
B26USB_D_SSRX_NDigital
Receive signal differential pairs for SuperSpeed on port D (I USB SS, USB SS, PU/PD: AC coupled off module)
B27GNDGround
Module Signal and power return and GND reference (P)
B28GNDGround
Module Signal and power return and GND reference (P)
B29VCC_8_TESTPower
Module power voltage testpoint (PO)
B30GNDGround
Module Signal and power return and GND reference (P)
B31eDP_A_LANE1_PDigital
Primary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module)
B32eDP_A_LANE1_NDigital
Primary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module)
B33GNDGround
Module Signal and power return and GND reference (P)
B34eDP_A_LANE3_PDigital
Primary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module)
B35eDP_A_LANE3_NDigital
Primary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module)
C1CSI_A_DATA0_NDigital
CSI differential input (point to point) (I LVDS D-PHY/ I LVDS M-PHY)
C2CAM_MCKDigital
Master clock output (O CMOS, 1.8V, PU/PD: shared with CAM_B)
C3CAM_A_SDA/ CSI_A_TX_NDigital
I2C data for serial camera data support link or differential data lane (I/O OD CMOS / O LVDS M-PHY, 1.8V, PU/PD: PU 2.2K, MIPI-CSI 2.0 mode uses CAM_A_SDA MIPI-CSI 3.0 mode uses CSI_A_TX_N)
C4CAM_A_SCL/ CSI_A_TX_PDigital
I2C clock for serial camera data support link or differential data lane (I/O OD CMOS / O LVDS M-PHY, 1.8V, PU/PD: PU 2.2K, MIPI-CSI 2.0 mode uses CAM_A_SCL MIPI-CSI 3.0 mode uses CSI_A_TX_P)
C5VCC_6_TESTPower
Module power voltage test point (PO)
C6ETH_B_MDCDigital
Management bus clock signal for Ethernet B (O CMOS, 1.8V/2.5V/3.3V, PU/PD: Optional use)
C7ETH_B_MDIODigital
Management bus data signal for Ethernet B (I/O CMOS, 1.8V/2.5V/3.3V, PU/PD: Optional use)
C8USB_C_OC#Digital
USB over-current for port C (I OD CMOS, 1.8V, PU/PD: PU 10k)
C9USB_C_VBUSDigital
USB port 0 port power detection (I USB VBUS 5V, USB VBUS 5V)
C10USB_C_ENDigital
Power enable for USB VBUS voltage (O CMOS, 1.8V)
C11GNDGround
Module Signal and power return and GND reference (P)
C13UART_A_RTSDigital
"Request to Send" handshake line for port A (O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
C14UART_A_CTSDigital
"Clear to Send" handshake line for port A (I CMOS, VCC_OUT_IO, PU/PD: 1.8V)
C15COM_AREA_15Digital
Main antenna test point
C16Vendor DefinedDigital
Defined by module manufacturer
C17COM_AREA_16Digital
Main antenna test point
C18TEST_GENERICDigital
General purpose for testing (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V, The TEST_GENERIC function should be specified by module vendor.)
C19COM_AREA_17Digital
Auxiliary antenna test point
C20SDIO_A_IOPWRPower
SDIO A Voltage. It is used to provide the IO Voltage Level (PO, 1.8V or 3.3V, PU/PD: Minimum current: 100mA)
C21COM_AREA_18Digital
Auxiliary antenna test point
C22UART_D_RXDigital
Asynchronous serial data input port D (I CMOS, VCC_OUT_IO, PU/PD: 1.8V)
C23UART_D_TXDigital
Asynchronous serial data output port D (O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
C25GNDGround
Module Signal and power return and GND reference (P)
C26USB_D_ENDigital
Power enable for USB VBUS voltage (O CMOS, 1.8V)
C27USB_D_VBUSDigital
USB port 0 port power detection (I USB VBUS 5V, USB VBUS 5V)
C28USB_D_OC#Digital
USB over-current for port D (I OD CMOS, 1.8V, PU/PD: PU 10k)
C29SPI_C_SDIDigital
SPI C Serial Data Input (I CMOS, 1.8V)
C30SPI_C_CS0#Digital
SPI C Master Chip Select 0 (O CMOS, 1.8V)
C31eDP_A_BL_PWMDigital
Primary eDP panel brightness control through pulse width modulation (O CMOS, 1.8V)
C32GNDGround
Module Signal and power return and GND reference (P)
C33eDP_A_AUX_PDigital
Primary bidirectional eDP channel used for link management and device control (I/O LVDS DP, PD 100k, PU/PD: AC coupled off module)
C34eDP_A_AUX_NDigital
Primary bidirectional eDP channel used for link management and device control (I/O LVDS DP, PD 100k, PU/PD: AC coupled off module)
C35GNDGround
Module Signal and power return and GND reference (P)
D1GNDGround
Module Signal and power return and GND reference (P)
D2ETH_B_(R)(G)MII_CRSDigital
Carrier Sense port B (I CMOS, 1.8V/2.5V/3.3V)
D3GPIO_C_0Digital
General purpose I/O Contact C0 (I/O CMOS, 1.8V)
D4GPIO_C_1Digital
General purpose I/O Contact C1 (I/O CMOS, 1.8V)
D5GNDGround
Module Signal and power return and GND reference (P)
D6Vendor DefinedDigital
Defined by module manufacturer
D7Vendor DefinedDigital
Defined by module manufacturer
D8GNDGround
Module Signal and power return and GND reference (P)
D9USB_C_IDDigital
Input Contact to announce OTG device insertion on USB 2.0 port (I OD CMOS, 1.8V, PU/PD: PU 10k)
D10USB_C_D_PDigital
USB differential data pairs for port C (I/O USB, USB)
D11USB_C_D_NDigital
USB differential data pairs for port C (I/O USB, USB)
D13UART_B_TXDigital
Asynchronous serial data output port B (O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
D14UART_B_RXDigital
Asynchronous serial data input port B (I CMOS, VCC_OUT_IO, PU/PD: 1.8V)
D15UART_B_RTSDigital
"Request to Send" handshake line for port B (O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
D16UART_B_CTSDigital
"Clear to Send" handshake line for port B (I CMOS, VCC_OUT_IO, PU/PD: 1.8V)
D17GPIO_A_0Digital
General purpose I/O Contact A0 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
D18GNDGround
Module Signal and power return and GND reference (P)
D19GPIO_B_0Digital
General purpose I/O Contact B0 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
D20SDIO_A_WPDigital
SDIO A Write Protect. This signal denotes the state of the write- protect tab on SD cards. (I OD CMOS, 1.8V or 3.3V, PU/PD: PU 10k, Tie to GND on carrier, if not used)
D21SDIO_A_PWR_ENDigital
SDIO A Power Enable. This signal is used to enable the power being supplied to a SD/MMC card device. (O CMOS, 1.8V or 3.3V)
D22UART_CON_RXDigital
Asynchronous serial data input port console (I CMOS, VCC_OUT_IO, PU/PD: 1.8V)
D23UART_CON_TXDigital
Asynchronous serial data output port console (O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
D25USB_D_D_PDigital
USB differential data pairs for port D (I/O USB, USB)
D26USB_D_D_NDigital
USB differential data pairs for port D (I/O USB, USB)
D27USB_D_IDDigital
Input Contact to announce OTG device insertion on USB 2.0 port (I OD CMOS, 1.8V, PU/PD: PU 10k)
D28GNDGround
Module Signal and power return and GND reference (P)
D29SPI_C_SCKDigital
SPI C Serial Data Clock (O CMOS, 1.8V)
D30SPI_C_SDODigital
SPI C Serial Data Output (O CMOS, 1.8V)
D31eDP_A_BL_ENDigital
Primary eDP panel backlight enable, active high (O CMOS, 1.8V)
D32eDP_A_AUX_SELDigital
Strapping signal to enable either HDMI or DP output (I CMOS, 1.8V, PU/PD: PD 1M, Pulled to GND on Carrier for DP operation in Dual Mode (DP++) implementations. Driven to 1.8V on carrier for HDMI mode Module must tolerate high level in stand-by mode)
D33eDP_A_HPDDigital
Detection of Hot Plug / Unplug of primary eDP display and notification of the link layer. (I CMOS, 1.8V, PU/PD: PD 1M, Module must tolerate high level in stand-by mode)
D34GNDGround
Module Signal and power return and GND reference (P)
D35eDP_B_LANE0_PDigital
Secondary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module)
E1ETH_B_(R)(G)MII_COLDigital
Collision detect (half speed only) port B (I CMOS, 1.8V/2.5V/3.3V)
E2GNDGround
Module Signal and power return and GND reference (P)
E3GPIO_C_2/ CAM_B_PWRDigital
Camera 1 Power Enable, active high output. (O CMOS, 1.8V)
E4GPIO_C_3/ CAM_B_RST#Digital
Camera 1 reset, active low output (O CMOS, 1.8V)
E15GNDGround
Module Signal and power return and GND reference (P)
E16ETH_A_(R)(G)MII_CRSDigital
Carrier Sense port A (I CMOS, 1.8V/2.5V/3.3V)
E17GPIO_A_1Digital
General purpose I/O Contact A1 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
E18PWM_0/ DISP_BL_PWMDigital
Primary Display brightness control through pulse width modulation (O CMOS, 1.8V)
E19GPIO_B_1Digital
General purpose I/O Contact B1 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
E20SDIO_A_CMDDigital
SDIO A Command/Response. This signal is used for card initialization and for command transfers. During initialization mode this signal is open drain. During command transfer this signal is in push-pull mode. (I/O CMOS, 1.8V or 3.3V)
E21GNDGround
Module Signal and power return and GND reference (P)
E32eDP_B_BL_ENDigital
Secondary eDP panel backlight enable, active high (O CMOS, 1.8V)
E33eDP_B_BL_PWMDigital
Secondary eDP panel brightness control through pulse width modulation (O CMOS, 1.8V)
E34eDP_B_LANE1_PDigital
Secondary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module)
E35eDP_B_LANE0_NDigital
Secondary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module)
F1ETH_B_(S)(R)(G)MII_TXD1Digital
Transmit data bit 1 port B (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _N when used as differential)
F2ETH_B_(S)(R)(G)MII_TXD3Digital
Transmit data bit 3 port B (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _N when used as differential)
F3GPIO_C_4/ DISP_VDD_ENDigital
Primary Display power enable, active high (O CMOS, 1.8V)
F4GPIO_C_5/ DISP_BL_ENDigital
Primary Display backlight enable, active high (O CMOS, 1.8V)
F15ETH_A_(R)(G)MII_COLDigital
Collision detect (half speed only) port A (I CMOS, 1.8V/2.5V/3.3V)
F16GNDGround
Module Signal and power return and GND reference (P)
F17GPIO_A_2Digital
General purpose I/O Contact A2 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
F18PWM_1Digital
Pulse width modulation 1 (O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
F19GPIO_B_2Digital
General purpose I/O Contact B2 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
F20GNDGround
Module Signal and power return and GND reference (P)
F21SDIO_A_CLKDigital
SDIO A Clock. With each cycle of this signal a one-bit transfer on the command and each data line occurs. (O CMOS, 1.8V or 3.3V)
F32eDP_B_AUX_SELDigital
Auxilary Selection (I CMOS, 1.8V, PU/PD: PD 1M, Pulled to GND on Carrier for DP operation in Dual Mode (DP++) implementations. Driven to 1.8V on carrier for HDMI mode Module must tolerate high level in stand-by mode)
F33GNDGround
Module Signal and power return and GND reference (P)
F34eDP_B_LANE1_NDigital
Secondary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module)
F35GNDGround
Module Signal and power return and GND reference (P)
G1ETH_B_(S)(R)(G)MII_TXD0Digital
Transmit data bit 0 (transmitted first) port B (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _P when used as differential)
G2ETH_B_(S)(R)(G)MII_TXD2Digital
Transmit data bit 2 port B (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _P when used as differential)
G3GPIO_C_6/ CAM_A_PWRDigital
Camera Power Enable, active high output. (O CMOS, 1.8V)
G4GPIO_C_7/ CAM_A_RST#Digital
Camera reset, active low output (O CMOS, 1.8V)
G15ETH_A_(S)(R)(G)MII_TXD1Digital
Transmit data bit 1 port A (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _N when used as differential)
G16ETH_A_(S)(R)(G)MII_TXD3Digital
Transmit data bit 3 port A (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _N when used as differential)
G17GPIO_A_3Digital
General purpose I/O Contact A3 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
G18PWM_2Digital
Pulse width modulation 2 (O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
G19GPIO_B_3Digital
General purpose I/O Contact B3 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
G20SDIO_A_D0Digital
SDIO A Data lines. These signals operate in push-pull mode. (I/O CMOS, 1.8V or 3.3V)
G21SDIO_A_D1Digital
SDIO A Data lines. These signals operate in push-pull mode. (I/O CMOS, 1.8V or 3.3V)
G32eDP_B_HPDDigital
Detection of Hot Plug / Unplug of secondary eDP display and notification of the link layer. (I CMOS, 1.8V, PU/PD: PD 1M, Module must tolerate high level in stand-by mode)
G33eDP_B_AUX_PDigital
Secondary bidirectional eDP channel used for link management and device control (I/O LVDS DP, PD 100k, PU/PD: AC coupled off module)
G34GNDGround
Module Signal and power return and GND reference (P)
G35eDP_B_LANE2_PDigital
Secondary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module)
H1ETH_B_(R)(G)MII_TX_CLKDigital
Transmit clock port B (I/O CMOS, 1.8V/2.5V/3.3V)
H2GNDGround
Module Signal and power return and GND reference (P)
H3RGB_CS#Digital
Chip select (O CMOS, 3.3V)
H4GNDGround
Module Signal and power return and GND reference (P)
H15ETH_A_(S)(R)(G)MII_TXD0Digital
Transmit data bit 0 (transmitted first) port A (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _P when used as differential)
H16ETH_A_(S)(R)(G)MII_TXD2Digital
Transmit data bit 2 port A (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _P when used as differential)
H17GPIO_A_4Digital
General purpose I/O Contact A4 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
H18PWM_3Digital
Pulse width modulation 3 (O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
H19GPIO_B_4Digital
General purpose I/O Contact B4 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
H20SDIO_A_D2Digital
SDIO A Data lines. These signals operate in push-pull mode. (I/O CMOS, 1.8V or 3.3V)
H21SDIO_A_D3Digital
SDIO A Data lines. These signals operate in push-pull mode. (I/O CMOS, 1.8V or 3.3V)
H32GNDGround
Module Signal and power return and GND reference (P)
H33eDP_B_AUX_NDigital
Secondary bidirectional eDP channel used for link management and device control (I/O LVDS DP, PD 100k, PU/PD: AC coupled off module)
H34eDP_B_LANE3_PDigital
Secondary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module)
H35eDP_B_LANE2_NDigital
Secondary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module)
J1ETH_B_(S)(R)(G)MII_RXD0Digital
Receive data bit 0 (received first) port B (I CMOS, 1.8V/2.5V/3.3V, PU/PD: _P when used as differential)
J2ETH_B_(R)(G)MII_TX_EN(_ER)Digital
Transmit enable (Error) port B (O CMOS, 1.8V/2.5V/3.3V)
J3RGB_RESET#Digital
Global Reset (O CMOS, 3.3V)
J4RGB_DEDigital
Data Enable (O CMOS, 3.3V)
J15ETH_A_(R)(G)MII_TX_CLKDigital
Transmit clock port A (I/O CMOS, 1.8V/2.5V/3.3V)
J16GNDGround
Module Signal and power return and GND reference (P)
J17GPIO_A_5Digital
General purpose I/O Contact A5 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
J18PWM_4Digital
Pulse width modulation 4 (O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
J19GPIO_B_5Digital
General purpose I/O Contact B5 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
J20GNDGround
Module Signal and power return and GND reference (P)
J21SDIO_A_CD#Digital
SDIO A Card Detect. This signal indicates when a SDIO/MMC card is present. (I OD CMOS, 1.8V or 3.3V, PU/PD: PU 10k)
J32CSI_B_CLOCK_NDigital
CSI differential clock input (point to point) (I LVDS D-PHY)
J33GNDGround
Module Signal and power return and GND reference (P)
J34eDP_B_LANE3_NDigital
Secondary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module)
J35GNDGround
Module Signal and power return and GND reference (P)
K1ETH_B_(S)(R)(G)MII_RXD1Digital
Receive data bit 1 port B (I CMOS, 1.8V/2.5V/3.3V, PU/PD: _N when used as differential)
K2ETH_B_(R)(G)MII_RX_ERDigital
Receive error port B (I CMOS, 1.8V/2.5V/3.3V)
K3RGB_HSYNCDigital
horizontal synch (O CMOS, 3.3V)
K4RGB_DISPDigital
Display ON/OFF (O CMOS, 3.3V)
K15ETH_A_(S)(R)(G)MII_RXD0Digital
Receive data bit 0 (received first) port A (I CMOS, 1.8V/2.5V/3.3V, PU/PD: _P when used as differential)
K16ETH_A_(R)(G)MII_TX_EN(_ER)Digital
Transmit enable (Error) port A (O CMOS, 1.8V/2.5V/3.3V)
K17GPIO_A_6/ SPI_A_CS1#Digital
General purpose I/O Contact A6 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V, Dual function: SPI_A_CS1#)
K18PWM_5Digital
Pulse width modulation 5 (O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
K19GPIO_B_6Digital
General purpose I/O Contact B6 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
K20SDIO_B_CLKDigital
SDIO B Clock. With each cycle of this signal a one-bit transfer on the command and each data line occurs. (O CMOS, 1.8V or 3.3V)
K21SDIO_B_CMDDigital
SDIO B Command/Response. This signal is used for card initialization and for command transfers. During initialization mode (I/O CMOS, 1.8V or 3.3V)
K32GNDGround
Module Signal and power return and GND reference (P)
K33CSI_B_CLOCK_PDigital
CSI differential clock input (point to point) (I LVDS D-PHY)
K34GNDGround
Module Signal and power return and GND reference (P)
K35PCIe_B_HSO0_PDigital
Differential PCIe link B transmit data pair (O LVDS PCIE, AC coupled off module)
L1ETH_B_(R)(G)MII_RX_DV(_ER)Digital
Receive data valid (Error) port B (I CMOS, 1.8V/2.5V/3.3V)
L2GNDGround
Module Signal and power return and GND reference (P)
L3RGB_VSYNCDigital
Vertical synch (O CMOS, 3.3V)
L4GNDGround
Module Signal and power return and GND reference (P)
L15ETH_A_(S)(R)(G)MII_RXD1Digital
Receive data bit 1 port A (I CMOS, 1.8V/2.5V/3.3V, PU/PD: _N when used as differential)
L16ETH_A_(R)(G)MII_RX_ERDigital
Receive error port A (I CMOS, 1.8V/2.5V/3.3V)
L17GPIO_A_7/ SPI_B_CS1#Digital
General purpose I/O Contact A7 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V, Dual function: SPI_B_CS1#)
L18GNDGround
Module Signal and power return and GND reference (P)
L19GPIO_B_7Digital
General purpose I/O Contact B7 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
L20SDIO_B_D0Digital
SDIO B Data lines. These signals operate in push-pull mode. (I/O CMOS, 1.8V or 3.3V)
L21SDIO_B_D1Digital
SDIO B Data lines. These signals operate in push-pull mode. (I/O CMOS, 1.8V or 3.3V)
L32CSI_B_DATA0_NDigital
CSI differential input (point to point) (I LVDS D-PHY/ I LVDS M-PHY)
L33PCIe_B_PERST#Digital
PCIe Port B reset output (O CMOS, 1.8V)
L34PCIe_B_HSI0_PDigital
Differential PCIe link B receive data pair (I LVDS PCIE, AC coupled off module)
L35PCIe_B_HSO0_NDigital
Differential PCIe link B transmit data pair (O LVDS PCIE, AC coupled off module)
M1ETH_B_(R)(G)MII_RXD2Digital
Receive data bit 2 port B (I CMOS, 1.8V/2.5V/3.3V)
M2ETH_B_SDPDigital
Ethernet port B System Defined Contact (I/O CMOS, 1.8V/2.5V/3.3V)
M3RGB_B5Digital
Blue data bit 5 (O CMOS, 3.3V)
M4RGB_(PIXEL)CLKDigital
Pixel clock signal (O CMOS, 3.3V)
M15ETH_A_(R)(G)MII_RX_DV(_ER)Digital
Receive data valid port A (I CMOS, 1.8V/2.5V/3.3V)
M16GNDGround
Module Signal and power return and GND reference (P)
M17ETH_IOPWRPower
ETH voltage. It is used to provide the IO Voltage Level for all Ethernet interfaces. (PO, 1.8V/2.5V/3.3V, PU/PD: Minimum current: 100mA)
M18ADC_0Analog
Analog Digital Converter 0 (Analog, 0V – 1.8V)
M19VCC_2_TESTPower
Module power voltage testpoint (PO)
M20GNDGround
Module Signal and power return and GND reference (P)
M21SDIO_B_D2Digital
SDIO B Data lines. These signals operate in push-pull mode. (I/O CMOS, 1.8V or 3.3V)
M32GNDGround
Module Signal and power return and GND reference (P)
M33CSI_B_DATA0_PDigital
CSI differential input (point to point) (I LVDS D-PHY / I LVDS M-PHY)
M34PCIe_B_HSI0_NDigital
Differential PCIe link B receive data pair (I LVDS PCIE, AC coupled off module)
M35GNDGround
Module Signal and power return and GND reference (P)
N1ETH_B_(R)(G)MII_RXD3Digital
Receive data bit 3 port B (I CMOS, 1.8V/2.5V/3.3V)
N2RESERVEDNC
Reserved for future use (NC)
N3RGB_B3Digital
Blue data bit 3 (O CMOS, 3.3V)
N4RGB_B4Digital
Blue data bit 4 (O CMOS, 3.3V)
N15ETH_A_(R)(G)MII_RXD2Digital
Receive data bit 2 port A (I CMOS, 1.8V/2.5V/3.3V)
N16ETH_A_SDPDigital
Ethernet port A System Defined Contact (I/O CMOS, 1.8V/2.5V/3.3V)
N17JTAG_TCK(SWCLK)Digital
Test Clock (I CMOS, VCC_OUT_IO, PU/PD: 1.8V)
N18ADC_1Analog
Analog Digital Converter 1 (Analog, 0V – 1.8V)
N19JTAG_TMS(SWDIO)Digital
Test Mode Select (I CMOS, VCC_OUT_IO, PU/PD: 1.8V)
N20SDIO_B_D3Digital
SDIO B Data lines. These signals operate in push-pull mode. (I/O CMOS, 1.8V or 3.3V)
N21SDIO_B_D4Digital
SDIO B Data lines. These signals operate in push-pull mode. (I/O CMOS, 1.8V or 3.3V)
N32CSI_B_DATA1_NDigital
CSI differential input (point to point) (I LVDS D-PHY / I LVDS M-PHY)
N33ETH_CDE_MDCDigital
Management bus clock signal for Ethernet C/D/E (O CMOS, 1.8V/2.5V/3.3V, PU/PD: Optional use)
N34GNDGround
Module Signal and power return and GND reference (P)
N35ETH_C_(R)(G)MII_TX_CLKDigital
Transmit clock port C (I/O CMOS, 1.8V/2.5V/3.3V)
P1ETH_B_(R)(G)MII_RX_CLKDigital
Receive clock port B (I/O CMOS, 1.8V/2.5V/3.3V)
P2GNDGround
Module Signal and power return and GND reference (P)
P3RGB_B2Digital
Blue data bit 2 (O CMOS, 3.3V)
P4GNDGround
Module Signal and power return and GND reference (P)
P15ETH_A_(R)(G)MII_RXD3Digital
Receive data bit 3 port A (I CMOS, 1.8V/2.5V/3.3V)
P16Vendor DefinedDigital
Defined by module manufacturer
P17JTAG_TDIDigital
Test Data Input (I CMOS, VCC_OUT_IO, PU/PD: 1.8V)
P18GNDGround
Module Signal and power return and GND reference (P)
P19JTAG_RTCKDigital
Returned Test Clock (O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
P20SDIO_B_D5Digital
SDIO B Data lines. These signals operate in push-pull mode. (I/O CMOS, 1.8V or 3.3V)
P21SDIO_B_D6Digital
SDIO B Data lines. These signals operate in push-pull mode. (I/O CMOS, 1.8V or 3.3V)
P32CSI_B_DATA1_PDigital
CSI differential input (point to point) (I LVDS D-PHY / I LVDS M-PHY)
P33ETH_CDE_MDIODigital
Management bus data signal for Ethernet C/D/E (I/O CMOS, 1.8V/2.5V/3.3V, PU/PD: Optional use)
P34CSI_B_DATA2_NDigital
CSI differential input (point to point) (I LVDS D-PHY / I LVDS M-PHY)
P35ETH_C_(R)(G)MII_RXD3Digital
Receive data bit 3 port C (I CMOS, 1.8V/2.5V/3.3V)
R1GNDGround
Module Signal and power return and GND reference (P)
R2PCIe_SM_ALERT#Digital
SMBus Alert# (interrupt) signal (I OD CMOS, 1.8V, PU/PD: PU 2k2)
R3RGB_B1Digital
Blue data bit 1 (O CMOS, 3.3V)
R4RGB_B0Digital
Blue data bit 0 (O CMOS, 3.3V)
R15ETH_A_(R)(G)MII_RX_CLKDigital
Receive clock port A (I/O CMOS, 1.8V/2.5V/3.3V)
R16GNDGround
Module Signal and power return and GND reference (P)
R17JTAG_TDO(SWO)Digital
Test Data Output (O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
R18BOOT_SEL1#Digital
I OD CMOS (1.8V, PU 10k, PU/PD: The boot medium is the choice of the module vendor.)
R19JTAG_nTRSTDigital
Test Reset, Active Low (I CMOS, VCC_OUT_IO, PU/PD: 1.8V)
R20GNDGround
Module Signal and power return and GND reference (P)
R21SDIO_B_D7Digital
SDIO B Data lines. These signals operate in push-pull mode. (I/O CMOS, 1.8V or 3.3V)
R32GNDGround
Module Signal and power return and GND reference (P)
R33CSI_B_DATA2_PDigital
CSI differential input (point to point) (I LVDS D-PHY / I LVDS M-PHY)
R34ETH_C_SDPDigital
Ethernet port C System Defined Contact (I/O CMOS, 1.8V/2.5V/3.3V)
R35ETH_C_(R)(G)MII_RXD2Digital
Receive data bit 2 port C (I CMOS, 1.8V/2.5V/3.3V)
T1PCIe_SMCLKDigital
System management I2C bus CLK (O OD CMOS, 1.8V, PU/PD: PU 2k2)
T2PCIe_WAKE#Digital
PCIe wake up interrupt to host – common to PCIe links A, B, C, D (I OD CMOS, 1.8V, PU/PD: PU 10k)
T3RGB_G4Digital
Green data bit 4 (O CMOS, 3.3V)
T4RGB_G5Digital
Green data bit 5 (O CMOS, 3.3V)
T15ETH_MDIODigital
Management bus data signal for Ethernet (I/O CMOS, 1.8V/2.5V/3.3V, PU/PD: Can be used for all ETH ports or for A exclusively)
T16ETH_MDCDigital
Management bus clock signal for Ethernet (O CMOS, 1.8V/2.5V/3.3V, PU/PD: Can be used for all ETH ports or for A exclusively)
T17FORCE_RECOVERY#Digital
If low on carrier board module enters recovery mode. (I OD CMOS, 1.8V, PU/PD: PU 10k, The recovery mode should be specified by module vendor.)
T18I2S_B_LRCLKDigital
I2S Left & Right synchronization clock (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V, Module Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode)
T19I2S_B_BITCLKDigital
I2S Digital audio clock (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V, Module Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode)
T20SDIO_B_IOPWRPower
SDIO B Voltage. It is used to provide the IO Voltage Level (PO, 1.8V or 3.3V, PU/PD: Minimum current: 100mA)
T21SDIO_B_CD#Digital
SDIO B Card Detect. This signal indicates when a SDIO/MMC card is present. (I OD CMOS, 1.8V or 3.3V, PU/PD: PU 10k)
T32CSI_B_DATA3_NDigital
CSI differential input (point to point) (I LVDS D-PHY / I LVDS M-PHY)
T33CSI_B_DATA3_PDigital
CSI differential input (point to point) (I LVDS D-PHY / I LVDS M-PHY)
T34GNDGround
Module Signal and power return and GND reference (P)
T35ETH_C_(R)(G)MII_RX_DV(_ER)Digital
Receive data valid (Error) port C (I CMOS, 1.8V/2.5V/3.3V)
U1PCIe_SMDATDigital
System management I2C bus DATA (I/O OD CMOS, 1.8V, PU/PD: PU 2k2)
U2GNDGround
Module Signal and power return and GND reference (P)
U3RGB_G3Digital
Green data bit 3 (O CMOS, 3.3V)
U4GNDGround
Module Signal and power return and GND reference (P)
U15SPI_A_SDI_(IO1)Digital
SPI_A_SDI_(IO1)
U16SPI_A_SCKDigital
SPI A Serial Data Clock (O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
U17RESET_IN#Digital
Reset input from Carrier board. Carrier drives low to force a Module reset, floats the line otherwise. (I OD CMOS, 1.8V, PU/PD: PU 10K)
U18VCC_OUT_IOPower
Provides IO voltage level for several interfaces to connect (PO, 1.8V/3.3V, PU/PD: 1.8V/3.3V on size 0, 1.8V on all other sizes – minimum current: 100 mA)
U19BOOT_SEL0#Digital
I OD CMOS (1.8V, PU 10k, PU/PD: The boot medium is the choice of the module vendor.)
U20SDIO_B_WPDigital
SDIO B Write Protect. This signal denotes the state of the write- protect tab on SD cards. (I OD CMOS, 1.8V or 3.3V, PU/PD: PU 10k, Tie to GND on carrier, if not used)
U21SDIO_B_PWR_ENDigital
SDIO B Power Enable. This signal is used to enable the power being supplied to a SD/MMC card device. (O CMOS, 1.8V or 3.3V)
U32GPIO_D_0Digital
General purpose I/O Contact D0 (I/O CMOS, 1.8V)
U33GPIO_D_1Digital
General purpose I/O Contact D1 (I/O CMOS, 1.8V)
U34ETH_C_(R)(G)MII_RX_ERDigital
Receive error port C (I CMOS, 1.8V/2.5V/3.3V)
U35ETH_C_(S)(R)(G)MII_RXD1Digital
Receive data bit 1 port C (I CMOS, 1.8V/2.5V/3.3V, PU/PD: _N when used as differential)
V1GNDGround
Module Signal and power return and GND reference (P)
V2PCIe_A_PERST#Digital
PCIe Port A reset output (O CMOS, 1.8V)
V3RGB_G1Digital
Green data bit 1 (O CMOS, 3.3V)
V4RGB_G2Digital
Green data bit 2 (O CMOS, 3.3V)
V15SPI_A_SDO_(IO0)Digital
SPI_A_SDO_(IO0)
V16GNDGround
Module Signal and power return and GND reference (P)
V17CARRIER_PWR_ENDigital
Carrier board circuits should not be powered up until the module asserts the CARRIER_PWR_EN signal (O CMOS, 1.8V)
V18I2S_MCLKDigital
Master clock output to I2S codec(s) (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
V19I2S_B_DATA_INDigital
I2S B Digital audio Input (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
V20GNDGround
Module Signal and power return and GND reference (P)
V21I2S_A_DATA_INDigital
I2S A Digital audio Input (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
V32GPIO_D_2Digital
General purpose I/O Contact D2 (I/O CMOS, 1.8V)
V33GPIO_D_3Digital
General purpose I/O Contact D3 (I/O CMOS, 1.8V)
V34ETH_C_(R)(G)MII_TX_EN(_ER)Digital
Transmit enable (Error) port C (O CMOS, 1.8V/2.5V/3.3V)
V35ETH_C_(S)(R)(G)MII_RXD0Digital
Receive data bit 0 (received first) port C (I CMOS, 1.8V/2.5V/3.3V, PU/PD: _P when used as differential)
W1PCIe_REFCLK_PDigital
Differential PCIe reference clock output (O LVDS PCIE)
W2PCIe_CLKREQ#Digital
PCIe reference clock request (I OD CMOS, 1.8V, PU/PD: PU 10k)
W3GNDGround
Module Signal and power return and GND reference (P)
W4RGB_G0Digital
Green data bit 0 (O CMOS, 3.3V)
W15SPI_A_HOLD_(IO3)Digital
SPI_A_HOLD_(IO3)
W16SPI_A_WP_(IO2)Digital
SPI_A_WP_(IO2)
W17RTC_PWRPower
Low current RTC circuit backup power – 3.0V nominal. May be sourced from a Carrier based Lithium cell or Super Cap. (P, If RTC is implemented, Module Vendor should ensure proper function of RTC during active main supply if this pin is not used)
W18I2S_A_LRCLKDigital
I2S Left & Right synchronization clock (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V, Module Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode)
W19I2S_B_DATA_OUTDigital
I2S B Digital audio Output (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
W20I2S_A_BITCLKDigital
I2S Digital audio clock (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V, Module Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode)
W21I2S_A_DATA_OUTDigital
I2S A Digital audio Output (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
W32GPIO_D_4Digital
General purpose I/O Contact D4 (I/O CMOS, 1.8V)
W33GPIO_D_5Digital
General purpose I/O Contact D5 (I/O CMOS, 1.8V)
W34GNDGround
Module Signal and power return and GND reference (P)
W35ETH_C_(R)(G)MII_RX_CLKDigital
Receive clock port C (I/O CMOS, 1.8V/2.5V/3.3V)
Y1PCIe_REFCLK_NDigital
Differential PCIe reference clock output (O LVDS PCIE)
Y2GNDGround
Module Signal and power return and GND reference (P)
Y3VCC_5_TESTPower
Module power voltage test point (PO)
Y4RGB_R5Digital
Red data bit 5 (O CMOS, 3.3V)
Y5RGB_R4Digital
Red data bit 4 (O CMOS, 3.3V)
Y6RGB_R2Digital
Red data bit 2 (O CMOS, 3.3V)
Y7RGB_R0Digital
Red data bit 0 (O CMOS, 3.3V)
Y8VCC_IN_5VPower
Module power input voltage of 5V (P, Tolerance: 5V +-5%)
Y9VCC_IN_5VPower
Module power input voltage of 5V (P, Tolerance: 5V +-5%)
Y10VCC_IN_5VPower
Module power input voltage of 5V (P, Tolerance: 5V +-5%)
Y11VCC_IN_5VPower
Module power input voltage of 5V (P, Tolerance: 5V +-5%)
Y13CARRIER_STBY#Digital
The Module shall drive this signal low when the system is in a standby power state (O CMOS, 1.8V, PU/PD: Optional)
Y14RESET_OUT#Digital
Reset output from CPU to reset peripherals on Carrier. (O CMOS, 1.8V)
Y15SPI_A_CS0#Digital
SPI A Master Chip Select 0 (O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
Y16VCC_3_TESTPower
Module power voltage testpoint (PO)
Y17VCC_IN_5VPower
Module power input voltage of 5V – Primary voltage rail for size S, M and L modules (P, Tolerance: 5V +-5%)
Y18GNDGround
Module Signal and power return and GND reference (P)
Y19VCC_IN_3V3Power
Module power input voltage of 3.3V – Primary voltage rail for 0 size modules (P, Tolerance: 3.3V +- 5%)
Y20VCC_4_TESTPower
Module power voltage testpoint (PO)
Y21SPI_B_SCKDigital
SPI B Serial Data Clock (O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
Y22SPI_B_SDIDigital
SPI B Serial Data Input (I CMOS, VCC_OUT_IO, PU/PD: 1.8V)
Y23SPI_B_SDODigital
SPI B Serial Data Output (O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
Y25VCC_IN_5VPower
Module power input voltage of 5V (P, Tolerance: 5V +-5%)
Y26VCC_IN_5VPower
Module power input voltage of 5V (P, Tolerance: 5V +-5%)
Y27VCC_IN_5VPower
Module power input voltage of 5V (P, Tolerance: 5V +-5%)
Y28VCC_IN_5VPower
Module power input voltage of 5V (P, Tolerance: 5V +-5%)
Y29Vendor DefinedDigital
Defined by module manufacturer
Y30Vendor DefinedDigital
Defined by module manufacturer
Y31Vendor DefinedDigital
Defined by module manufacturer
Y32GPIO_D_6Digital
General purpose I/O Contact D6 (I/O CMOS, 1.8V)
Y33GPIO_D_7/ SPI_C_CS1#Digital
General purpose I/O Contact D7 (I/O CMOS, 1.8V, PU/PD: Dual function: SPI_C_CS1#)
Y34ETH_C_(S)(R)(G)MII_TXD2Digital
Transmit data bit 2 port C (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _P when used as differential)
Y35ETH_C_(S)(R)(G)MII_TXD0Digital
Transmit data bit 0 (transmitted first) port C (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _P when used as differential)
AA1GNDGround
Module Signal and power return and GND reference (P)
AA2RESERVEDNC
Reserved for future use (NC)
AA3DSI_TEDigital
DSI panel tearing effect signal (I CMOS, 1.8V, PU/PD: not used in LVDS mode)
AA4GNDGround
Module Signal and power return and GND reference (P)
AA5RGB_R3Digital
Red data bit 3 (O CMOS, 3.3V)
AA6RGB_R1Digital
Red data bit 1 (O CMOS, 3.3V)
AA7GNDGround
Module Signal and power return and GND reference (P)
AA8GNDGround
Module Signal and power return and GND reference (P)
AA9PWR_BTN#Digital
Power-button input from Carrier board. Carrier to float the line in in-active state. Active low, level sensitive. Should be de-bounced on the Module. (I OD CMOS, 1.8 to 5V, PU/PD: PU 10K)
AA10GNDGround
Module Signal and power return and GND reference (P)
AA11GNDGround
Module Signal and power return and GND reference (P)
AA13RESERVEDNC
Reserved for future use (NC)
AA14GNDGround
Module Signal and power return and GND reference (P)
AA15I2C_A_SCLDigital
I2C Port A Clock Signal (I/O OD CMOS, VCC_OUT_IO, PU/PD: 1.8V, PU 2k2)
AA16I2C_A_SDADigital
I2C Port A Data Signal (I/O OD CMOS, VCC_OUT_IO, PU/PD: 1.8V, PU 2k2)
AA17GNDGround
Module Signal and power return and GND reference (P)
AA18V_BATPower
Module power input battery voltage (P)
AA19GNDGround
Module Signal and power return and GND reference (P)
AA20I2C_B_SCLDigital
I2C Port B Clock Signal (I/O OD CMOS, VCC_OUT_IO, PU/PD: 1.8V, PU 2k2)
AA21I2C_B_SDADigital
I2C Port B Data Signal (I/O OD CMOS, VCC_OUT_IO, PU/PD: 1.8V, PU 2k2)
AA22GNDGround
Module Signal and power return and GND reference (P)
AA23SPI_B_CS0#Digital
SPI B Master Chip Select 0 (O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
AA25GNDGround
Module Signal and power return and GND reference (P)
AA26GNDGround
Module Signal and power return and GND reference (P)
AA27GNDGround
Module Signal and power return and GND reference (P)
AA28GNDGround
Module Signal and power return and GND reference (P)
AA29Vendor DefinedDigital
Defined by module manufacturer
AA30Vendor DefinedDigital
Defined by module manufacturer
AA31Vendor DefinedDigital
Defined by module manufacturer
AA32GNDGround
Module Signal and power return and GND reference (P)
AA33VCC_7_TESTPower
Module power voltage testpoint (PO)
AA34ETH_C_(S)(R)(G)MII_TXD3Digital
Transmit data bit 3 port C (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _N when used as differential)
AA35ETH_C_(S)(R)(G)MII_TXD1Digital
Transmit data bit 1 port C (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _N when used as differential)
AB1PCIe_A_HSI0_PDigital
Differential PCIe link A receive data pair (I LVDS PCIE, AC coupled off module)
AB2PCIe_A_HSI0_NDigital
Differential PCIe link A receive data pair (I LVDS PCIE, AC coupled off module)
AB3GNDGround
Module Signal and power return and GND reference (P)
AB4DSI_DATA3_P/ LVDS_A_LANE3_PDigital
DSI differential output (point to point) / LVDS channel A differential pair data lines (O LVDS D-PHY / O LVDS LCD, Alternate use: LVDS_A_ LANE3_P)
AB5DSI_DATA3_N/ LVDS_A_LANE3_NDigital
DSI differential output (point to point) / LVDS channel A differential pair data lines (O LVDS D-PHY / O LVDS LCD, Alternate use: LVDS_A_ LANE3_N)
AB6GNDGround
Module Signal and power return and GND reference (P)
AB7DSI_CLOCK_P/ LVDS_A_CLK_PDigital
DSI differential clock output (point to point) / LVDS channel A differential pair clock lines (O LVDS D-PHY / O LVDS LCD, Alternate use: LVDS_A_CLK_P)
AB8DSI_CLOCK_N/ LVDS_A_CLK_NDigital
DSI differential clock output (point to point) / LVDS channel A differential pair clock lines (O LVDS D-PHY / O LVDS LCD, Alternate use: LVDS_A_CLK_N)
AB9GNDGround
Module Signal and power return and GND reference (P)
AB10DSI_DATA0_P/ LVDS_A_LANE0_PDigital
DSI differential output (point to point) / LVDS channel A differential pair data lines (O LVDS D-PHY / O LVDS LCD, Alternate use: LVDS_A_LANE0_P)
AB11DSI_DATA0_N/ LVDS_A_LANE0_NDigital
DSI differential output (point to point) / LVDS channel A differential pair data lines (O LVDS D-PHY / O LVDS LCD, Alternate use: LVDS_A_LANE0_N)
AB13USB_A_D_NDigital
USB differential data pairs for port A (I/O USB, USB)
AB14USB_A_IDDigital
Input Contact to announce OTG device insertion on USB 2.0 port (I OD CMOS, 1.8V, PU/PD: PU 10k)
AB15GNDGround
Module Signal and power return and GND reference (P)
AB16USB_A_VBUSDigital
USB port 0 port power detection (I USB VBUS 5V, USB VBUS 5V)
AB17CAN_A_RXDigital
CAN port A Receive input (I CMOS, VCC_OUT_IO, PU/PD: 1.8V)
AB18V_BATPower
Module power input battery voltage (P)
AB19CAN_B_RXDigital
CAN port B Receive input (I CMOS, VCC_OUT_IO, PU/PD: 1.8V)
AB20USB_B_VBUSDigital
USB port 0 port power detection (I USB VBUS 5V, USB VBUS 5V)
AB21GNDGround
Module Signal and power return and GND reference (P)
AB22USB_B_IDDigital
Input Contact to announce OTG device insertion on USB 2.0 port (I OD CMOS, 1.8V, PU/PD: PU 10k)
AB23USB_B_D_NDigital
USB differential data pairs for port B (I/O USB, USB)
AB25CAM_B_SCL/ CSI_B_TX_PDigital
I2C clock for serial camera data support link or differential data lane (I/O OD CMOS / O LVDS M-PHY, 1.8V, PU/PD: PU 2.2K, MIPI-CSI 2.0 mode uses CAM_B_SCL MIPI-CSI 3.0 mode uses CSI_B_TX_P)
AB26CAM_B_SDA/ CSI_B_TX_NDigital
I2C data for serial camera data support link or differential data lane (I/O OD CMOS / O LVDS M-PHY, 1.8V, PU/PD: PU 2.2K, MIPI-CSI 2.0 mode uses CAM_B_SDA MIPI-CSI 3.0 mode uses CSI_B_TX_N)
AB27UFS_RESET#Digital
UFS reset output (O CMOS, 1.8V / 1.2V, PU/PD: USF 3.0 need 1.2V I/O level)
AB28GNDGround
Module Signal and power return and GND reference (P)
AB29UFS_TX1_PDigital
UFS differential output (point to point) (O LVDS UFS)
AB30UFS_TX1_NDigital
UFS differential output (point to point) (O LVDS UFS)
AB31GNDGround
Module Signal and power return and GND reference (P)
AB32UFS_RX1_PDigital
UFS differential input (point to point) (I LVDS UFS)
AB33UFS_RX1_NDigital
UFS differential input (point to point) (I LVDS UFS)
AB34GNDGround
Module Signal and power return and GND reference (P)
AB35ETH_C_(R)(G)MII_COLDigital
Collision detect (half speed only) port C (I CMOS, 1.8V/2.5V/3.3V)
AC2PCIe_A_HSO0_PDigital
Differential PCIe link A transmit data pair (O LVDS PCIE, AC coupled off module)
AC3PCIe_A_HSO0_NDigital
Differential PCIe link A transmit data pair (O LVDS PCIE, AC coupled off module)
AC4GNDGround
Module Signal and power return and GND reference (P)
AC5DSI_DATA2_P/ LVDS_A_LANE2_PDigital
DSI differential output (point to point) / LVDS channel A differential pair data lines (O LVDS D-PHY / O LVDS LCD, Alternate use: LVDS_A_ LANE2_P)
AC6DSI_DATA2_N/ LVDS_A_LANE2_NDigital
DSI differential output (point to point) / LVDS channel A differential pair data lines (O LVDS D-PHY / O LVDS LCD, Alternate use: LVDS_A_ LANE2_N)
AC7GNDGround
Module Signal and power return and GND reference (P)
AC8DSI_DATA1_P/ LVDS_A_LANE1_PDigital
DSI differential output (point to point) / LVDS channel A differential pair data lines (O LVDS D-PHY / O LVDS LCD, Alternate use: LVDS_A_ LANE1_P)
AC9DSI_DATA1_N/ LVDS_A_LANE1_NDigital
DSI differential output (point to point) / LVDS channel A differential pair data lines (O LVDS D-PHY / O LVDS LCD, Alternate use: LVDS_A_ LANE1_N)
AC10GNDGround
Module Signal and power return and GND reference (P)
AC14USB_A_D_PDigital
USB differential data pairs for port A (I/O USB, USB)
AC15USB_A_OC#Digital
USB over-current for port A (I OD CMOS, 1.8V, PU/PD: PU 10k)
AC16USB_A_ENDigital
Power enable for USB VBUS voltage (O CMOS, 1.8V)
AC17CAN_A_TXDigital
CAN port A Transmit output (O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
AC18DEBUG_ENDigital
Enables JTAG function (I CMOS, VCC_OUT_IO, PU/PD: 1.8V)
AC19CAN_B_TXDigital
CAN port B Transmit output (O CMOS, VCC_OUT_IO, PU/PD: 1.8V)
AC20USB_B_ENDigital
Power enable for USB VBUS voltage (O CMOS, 1.8V)
AC21USB_B_OC#Digital
USB over-current for port B (I OD CMOS, 1.8V, PU/PD: PU 10k)
AC22USB_B_D_PDigital
USB differential data pairs for port B (I/O USB, USB)
AC26UFS_CLKDigital
UFS reference clock output (O CMOS, 1.8V / 1.2 V, PU/PD: USF 3.0 need 1.2V I/O level)
AC27GNDGround
Module Signal and power return and GND reference (P)
AC28UFS_TX0_PDigital
UFS differential output (point to point) (O LVDS UFS)
AC29UFS_TX0_NDigital
UFS differential output (point to point) (O LVDS UFS)
AC30GNDGround
Module Signal and power return and GND reference (P)
AC31UFS_RX0_PDigital
UFS differential input (point to point) (I LVDS UFS)
AC32UFS_RX0_NDigital
UFS differential input (point to point) (I LVDS UFS)
AC33GNDGround
Module Signal and power return and GND reference (P)
AC34ETH_C_(R)(G)MII_CRSDigital
Carrier Sense port C (I CMOS, 1.8V/2.5V/3.3V)

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