OSM Size-L (Rev. 1.2) Pinout
SGeT Open Standard Module (OSM) V1.2 Size-L (Large, 45×45 mm) pinout specification with 662 LGA solder contacts featuring up to 5x Ethernet, PCIe x4, LVDS and extensive high-speed interfaces.
Aliase:OSM, Open Standard Module, OSM Size-L, OSM-L, OSM-LF, OSM-LE, SGeT OSM, Size Large
OSM Size-L (45×45mm)
662 Pins
Pin-Tabelle662
| Pin | Signal / Name | Typ | Alternative Funktionen |
|---|---|---|---|
| A2 | CSI_A_DATA1_N | Digital | CSI differential input (point to point) (I LVDS D-PHY / I LVDS M-PHY) |
| A3 | CSI_A_DATA1_P | Digital | CSI differential input (point to point) (I LVDS D-PHY / I LVDS M-PHY) |
| A4 | GND | Ground | Module Signal and power return and GND reference (P) |
| A5 | CSI_A_DATA2_N | Digital | CSI differential input (point to point) (I LVDS D-PHY / I LVDS M-PHY) |
| A6 | CSI_A_DATA2_P | Digital | CSI differential input (point to point) (I LVDS D-PHY / I LVDS M-PHY) |
| A7 | GND | Ground | Module Signal and power return and GND reference (P) |
| A8 | USB_C_SSTX_P | Digital | Transmit signal differential pairs for SuperSpeed on port C (O USB SS, USB SS, PU/PD: AC coupled off module) |
| A9 | USB_C_SSTX_N | Digital | Transmit signal differential pairs for SuperSpeed on port C (O USB SS, USB SS, PU/PD: AC coupled off module) |
| A10 | GND | Ground | Module Signal and power return and GND reference (P) |
| A14 | UART_A_RX | Digital | Asynchronous serial data input port A (I CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| A15 | COM_AREA_01 | Digital | Antenna Ground |
| A16 | COM_AREA_02 | Digital | LINK LED Channel 1 (O OD CMOS, 3.3V) |
| A17 | COM_AREA_03 | Digital | Antenna Ground |
| A18 | COM_AREA_04 | Digital | SYNC Trigger Signal Channel 0 (O CMOS, 3.3V) |
| A19 | COM_AREA_05 | Digital | Antenna Ground |
| A20 | COM_AREA_06 | Digital | Antenna Auxiliary Signal |
| A21 | COM_AREA_07 | Digital | Antenna Ground |
| A22 | UART_C_RX | Digital | Asynchronous serial data input port C (I CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| A26 | GND | Ground | Module Signal and power return and GND reference (P) |
| A27 | USB_D_SSTX_P | Digital | Transmit signal differential pairs for SuperSpeed on port D (O USB SS, USB SS, PU/PD: AC coupled off module) |
| A28 | USB_D_SSTX_N | Digital | Transmit signal differential pairs for SuperSpeed on port D (O USB SS, USB SS, PU/PD: AC coupled off module) |
| A29 | GND | Ground | Module Signal and power return and GND reference (P) |
| A30 | eDP_A_LANE0_P | Digital | Primary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module) |
| A31 | eDP_A_LANE0_N | Digital | Primary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module) |
| A32 | GND | Ground | Module Signal and power return and GND reference (P) |
| A33 | eDP_A_LANE2_P | Digital | Primary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module) |
| A34 | eDP_A_LANE2_N | Digital | Primary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module) |
| B1 | CSI_A_DATA0_P | Digital | CSI differential input (point to point) (I LVDS D-PHY / I LVDS M-PHY) |
| B2 | GND | Ground | Module Signal and power return and GND reference (P) |
| B3 | CSI_A_CLOCK_N | Digital | CSI differential clock input (point to point) (I LVDS D-PHY) |
| B4 | CSI_A_CLOCK_P | Digital | CSI differential clock input (point to point) (I LVDS D-PHY) |
| B5 | GND | Ground | Module Signal and power return and GND reference (P) |
| B6 | CSI_A_DATA3_N | Digital | CSI differential input (point to point) (I LVDS D-PHY / I LVDS M-PHY) |
| B7 | CSI_A_DATA3_P | Digital | CSI differential input (point to point) (I LVDS D-PHY / I LVDS M-PHY) |
| B8 | GND | Ground | Module Signal and power return and GND reference (P) |
| B9 | GND | Ground | Module Signal and power return and GND reference (P) |
| B10 | USB_C_SSRX_P | Digital | Receive signal differential pairs for SuperSpeed on port C (I USB SS, USB SS, PU/PD: AC coupled off module) |
| B11 | USB_C_SSRX_N | Digital | Receive signal differential pairs for SuperSpeed on port C (I USB SS, USB SS, PU/PD: AC coupled off module) |
| B13 | UART_A_TX | Digital | Asynchronous serial data output port A (O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| B15 | COM_AREA_08 | Digital | Antenna Ground |
| B16 | COM_AREA_09 | Digital | ACT LED Channel 1 (O OD CMOS, 3.3V) |
| B17 | COM_AREA_10 | Digital | Antenna Ground |
| B18 | COM_AREA_11 | Digital | SYNC Trigger Signal Channel 1 (O CMOS, 3.3V) |
| B19 | COM_AREA_12 | Digital | Antenna Ground |
| B20 | COM_AREA_13 | Digital | ACT LED Channel 0 (O OD CMOS, 3.3V) |
| B21 | COM_AREA_14 | Digital | Antenna Ground |
| B22 | Vendor Defined | Digital | Defined by module manufacturer |
| B23 | UART_C_TX | Digital | Asynchronous serial data output port C (O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| B25 | USB_D_SSRX_P | Digital | Receive signal differential pairs for SuperSpeed on port D (I USB SS, USB SS, PU/PD: AC coupled off module) |
| B26 | USB_D_SSRX_N | Digital | Receive signal differential pairs for SuperSpeed on port D (I USB SS, USB SS, PU/PD: AC coupled off module) |
| B27 | GND | Ground | Module Signal and power return and GND reference (P) |
| B28 | GND | Ground | Module Signal and power return and GND reference (P) |
| B29 | VCC_8_TEST | Power | Module power voltage testpoint (PO) |
| B30 | GND | Ground | Module Signal and power return and GND reference (P) |
| B31 | eDP_A_LANE1_P | Digital | Primary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module) |
| B32 | eDP_A_LANE1_N | Digital | Primary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module) |
| B33 | GND | Ground | Module Signal and power return and GND reference (P) |
| B34 | eDP_A_LANE3_P | Digital | Primary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module) |
| B35 | eDP_A_LANE3_N | Digital | Primary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module) |
| C1 | CSI_A_DATA0_N | Digital | CSI differential input (point to point) (I LVDS D-PHY/ I LVDS M-PHY) |
| C2 | CAM_MCK | Digital | Master clock output (O CMOS, 1.8V, PU/PD: shared with CAM_B) |
| C3 | CAM_A_SDA/ CSI_A_TX_N | Digital | I2C data for serial camera data support link or differential data lane (I/O OD CMOS / O LVDS M-PHY, 1.8V, PU/PD: PU 2.2K, MIPI-CSI 2.0 mode uses CAM_A_SDA MIPI-CSI 3.0 mode uses CSI_A_TX_N) |
| C4 | CAM_A_SCL/ CSI_A_TX_P | Digital | I2C clock for serial camera data support link or differential data lane (I/O OD CMOS / O LVDS M-PHY, 1.8V, PU/PD: PU 2.2K, MIPI-CSI 2.0 mode uses CAM_A_SCL MIPI-CSI 3.0 mode uses CSI_A_TX_P) |
| C5 | VCC_6_TEST | Power | Module power voltage test point (PO) |
| C6 | ETH_B_MDC | Digital | Management bus clock signal for Ethernet B (O CMOS, 1.8V/2.5V/3.3V, PU/PD: Optional use) |
| C7 | ETH_B_MDIO | Digital | Management bus data signal for Ethernet B (I/O CMOS, 1.8V/2.5V/3.3V, PU/PD: Optional use) |
| C8 | USB_C_OC# | Digital | USB over-current for port C (I OD CMOS, 1.8V, PU/PD: PU 10k) |
| C9 | USB_C_VBUS | Digital | USB port 0 port power detection (I USB VBUS 5V, USB VBUS 5V) |
| C10 | USB_C_EN | Digital | Power enable for USB VBUS voltage (O CMOS, 1.8V) |
| C11 | GND | Ground | Module Signal and power return and GND reference (P) |
| C13 | UART_A_RTS | Digital | "Request to Send" handshake line for port A (O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| C14 | UART_A_CTS | Digital | "Clear to Send" handshake line for port A (I CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| C15 | COM_AREA_15 | Digital | Main antenna test point |
| C16 | Vendor Defined | Digital | Defined by module manufacturer |
| C17 | COM_AREA_16 | Digital | Main antenna test point |
| C18 | TEST_GENERIC | Digital | General purpose for testing (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V, The TEST_GENERIC function should be specified by module vendor.) |
| C19 | COM_AREA_17 | Digital | Auxiliary antenna test point |
| C20 | SDIO_A_IOPWR | Power | SDIO A Voltage. It is used to provide the IO Voltage Level (PO, 1.8V or 3.3V, PU/PD: Minimum current: 100mA) |
| C21 | COM_AREA_18 | Digital | Auxiliary antenna test point |
| C22 | UART_D_RX | Digital | Asynchronous serial data input port D (I CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| C23 | UART_D_TX | Digital | Asynchronous serial data output port D (O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| C25 | GND | Ground | Module Signal and power return and GND reference (P) |
| C26 | USB_D_EN | Digital | Power enable for USB VBUS voltage (O CMOS, 1.8V) |
| C27 | USB_D_VBUS | Digital | USB port 0 port power detection (I USB VBUS 5V, USB VBUS 5V) |
| C28 | USB_D_OC# | Digital | USB over-current for port D (I OD CMOS, 1.8V, PU/PD: PU 10k) |
| C29 | SPI_C_SDI | Digital | SPI C Serial Data Input (I CMOS, 1.8V) |
| C30 | SPI_C_CS0# | Digital | SPI C Master Chip Select 0 (O CMOS, 1.8V) |
| C31 | eDP_A_BL_PWM | Digital | Primary eDP panel brightness control through pulse width modulation (O CMOS, 1.8V) |
| C32 | GND | Ground | Module Signal and power return and GND reference (P) |
| C33 | eDP_A_AUX_P | Digital | Primary bidirectional eDP channel used for link management and device control (I/O LVDS DP, PD 100k, PU/PD: AC coupled off module) |
| C34 | eDP_A_AUX_N | Digital | Primary bidirectional eDP channel used for link management and device control (I/O LVDS DP, PD 100k, PU/PD: AC coupled off module) |
| C35 | GND | Ground | Module Signal and power return and GND reference (P) |
| D1 | GND | Ground | Module Signal and power return and GND reference (P) |
| D2 | ETH_B_(R)(G)MII_CRS | Digital | Carrier Sense port B (I CMOS, 1.8V/2.5V/3.3V) |
| D3 | GPIO_C_0 | Digital | General purpose I/O Contact C0 (I/O CMOS, 1.8V) |
| D4 | GPIO_C_1 | Digital | General purpose I/O Contact C1 (I/O CMOS, 1.8V) |
| D5 | GND | Ground | Module Signal and power return and GND reference (P) |
| D6 | Vendor Defined | Digital | Defined by module manufacturer |
| D7 | Vendor Defined | Digital | Defined by module manufacturer |
| D8 | GND | Ground | Module Signal and power return and GND reference (P) |
| D9 | USB_C_ID | Digital | Input Contact to announce OTG device insertion on USB 2.0 port (I OD CMOS, 1.8V, PU/PD: PU 10k) |
| D10 | USB_C_D_P | Digital | USB differential data pairs for port C (I/O USB, USB) |
| D11 | USB_C_D_N | Digital | USB differential data pairs for port C (I/O USB, USB) |
| D13 | UART_B_TX | Digital | Asynchronous serial data output port B (O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| D14 | UART_B_RX | Digital | Asynchronous serial data input port B (I CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| D15 | UART_B_RTS | Digital | "Request to Send" handshake line for port B (O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| D16 | UART_B_CTS | Digital | "Clear to Send" handshake line for port B (I CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| D17 | GPIO_A_0 | Digital | General purpose I/O Contact A0 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| D18 | GND | Ground | Module Signal and power return and GND reference (P) |
| D19 | GPIO_B_0 | Digital | General purpose I/O Contact B0 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| D20 | SDIO_A_WP | Digital | SDIO A Write Protect. This signal denotes the state of the write- protect tab on SD cards. (I OD CMOS, 1.8V or 3.3V, PU/PD: PU 10k, Tie to GND on carrier, if not used) |
| D21 | SDIO_A_PWR_EN | Digital | SDIO A Power Enable. This signal is used to enable the power being supplied to a SD/MMC card device. (O CMOS, 1.8V or 3.3V) |
| D22 | UART_CON_RX | Digital | Asynchronous serial data input port console (I CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| D23 | UART_CON_TX | Digital | Asynchronous serial data output port console (O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| D25 | USB_D_D_P | Digital | USB differential data pairs for port D (I/O USB, USB) |
| D26 | USB_D_D_N | Digital | USB differential data pairs for port D (I/O USB, USB) |
| D27 | USB_D_ID | Digital | Input Contact to announce OTG device insertion on USB 2.0 port (I OD CMOS, 1.8V, PU/PD: PU 10k) |
| D28 | GND | Ground | Module Signal and power return and GND reference (P) |
| D29 | SPI_C_SCK | Digital | SPI C Serial Data Clock (O CMOS, 1.8V) |
| D30 | SPI_C_SDO | Digital | SPI C Serial Data Output (O CMOS, 1.8V) |
| D31 | eDP_A_BL_EN | Digital | Primary eDP panel backlight enable, active high (O CMOS, 1.8V) |
| D32 | eDP_A_AUX_SEL | Digital | Strapping signal to enable either HDMI or DP output (I CMOS, 1.8V, PU/PD: PD 1M, Pulled to GND on Carrier for DP operation in Dual Mode (DP++) implementations. Driven to 1.8V on carrier for HDMI mode Module must tolerate high level in stand-by mode) |
| D33 | eDP_A_HPD | Digital | Detection of Hot Plug / Unplug of primary eDP display and notification of the link layer. (I CMOS, 1.8V, PU/PD: PD 1M, Module must tolerate high level in stand-by mode) |
| D34 | GND | Ground | Module Signal and power return and GND reference (P) |
| D35 | eDP_B_LANE0_P | Digital | Secondary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module) |
| E1 | ETH_B_(R)(G)MII_COL | Digital | Collision detect (half speed only) port B (I CMOS, 1.8V/2.5V/3.3V) |
| E2 | GND | Ground | Module Signal and power return and GND reference (P) |
| E3 | GPIO_C_2/ CAM_B_PWR | Digital | Camera 1 Power Enable, active high output. (O CMOS, 1.8V) |
| E4 | GPIO_C_3/ CAM_B_RST# | Digital | Camera 1 reset, active low output (O CMOS, 1.8V) |
| E15 | GND | Ground | Module Signal and power return and GND reference (P) |
| E16 | ETH_A_(R)(G)MII_CRS | Digital | Carrier Sense port A (I CMOS, 1.8V/2.5V/3.3V) |
| E17 | GPIO_A_1 | Digital | General purpose I/O Contact A1 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| E18 | PWM_0/ DISP_BL_PWM | Digital | Primary Display brightness control through pulse width modulation (O CMOS, 1.8V) |
| E19 | GPIO_B_1 | Digital | General purpose I/O Contact B1 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| E20 | SDIO_A_CMD | Digital | SDIO A Command/Response. This signal is used for card initialization and for command transfers. During initialization mode this signal is open drain. During command transfer this signal is in push-pull mode. (I/O CMOS, 1.8V or 3.3V) |
| E21 | GND | Ground | Module Signal and power return and GND reference (P) |
| E32 | eDP_B_BL_EN | Digital | Secondary eDP panel backlight enable, active high (O CMOS, 1.8V) |
| E33 | eDP_B_BL_PWM | Digital | Secondary eDP panel brightness control through pulse width modulation (O CMOS, 1.8V) |
| E34 | eDP_B_LANE1_P | Digital | Secondary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module) |
| E35 | eDP_B_LANE0_N | Digital | Secondary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module) |
| F1 | ETH_B_(S)(R)(G)MII_TXD1 | Digital | Transmit data bit 1 port B (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _N when used as differential) |
| F2 | ETH_B_(S)(R)(G)MII_TXD3 | Digital | Transmit data bit 3 port B (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _N when used as differential) |
| F3 | GPIO_C_4/ DISP_VDD_EN | Digital | Primary Display power enable, active high (O CMOS, 1.8V) |
| F4 | GPIO_C_5/ DISP_BL_EN | Digital | Primary Display backlight enable, active high (O CMOS, 1.8V) |
| F15 | ETH_A_(R)(G)MII_COL | Digital | Collision detect (half speed only) port A (I CMOS, 1.8V/2.5V/3.3V) |
| F16 | GND | Ground | Module Signal and power return and GND reference (P) |
| F17 | GPIO_A_2 | Digital | General purpose I/O Contact A2 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| F18 | PWM_1 | Digital | Pulse width modulation 1 (O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| F19 | GPIO_B_2 | Digital | General purpose I/O Contact B2 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| F20 | GND | Ground | Module Signal and power return and GND reference (P) |
| F21 | SDIO_A_CLK | Digital | SDIO A Clock. With each cycle of this signal a one-bit transfer on the command and each data line occurs. (O CMOS, 1.8V or 3.3V) |
| F32 | eDP_B_AUX_SEL | Digital | Auxilary Selection (I CMOS, 1.8V, PU/PD: PD 1M, Pulled to GND on Carrier for DP operation in Dual Mode (DP++) implementations. Driven to 1.8V on carrier for HDMI mode Module must tolerate high level in stand-by mode) |
| F33 | GND | Ground | Module Signal and power return and GND reference (P) |
| F34 | eDP_B_LANE1_N | Digital | Secondary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module) |
| F35 | GND | Ground | Module Signal and power return and GND reference (P) |
| G1 | ETH_B_(S)(R)(G)MII_TXD0 | Digital | Transmit data bit 0 (transmitted first) port B (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _P when used as differential) |
| G2 | ETH_B_(S)(R)(G)MII_TXD2 | Digital | Transmit data bit 2 port B (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _P when used as differential) |
| G3 | GPIO_C_6/ CAM_A_PWR | Digital | Camera Power Enable, active high output. (O CMOS, 1.8V) |
| G4 | GPIO_C_7/ CAM_A_RST# | Digital | Camera reset, active low output (O CMOS, 1.8V) |
| G15 | ETH_A_(S)(R)(G)MII_TXD1 | Digital | Transmit data bit 1 port A (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _N when used as differential) |
| G16 | ETH_A_(S)(R)(G)MII_TXD3 | Digital | Transmit data bit 3 port A (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _N when used as differential) |
| G17 | GPIO_A_3 | Digital | General purpose I/O Contact A3 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| G18 | PWM_2 | Digital | Pulse width modulation 2 (O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| G19 | GPIO_B_3 | Digital | General purpose I/O Contact B3 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| G20 | SDIO_A_D0 | Digital | SDIO A Data lines. These signals operate in push-pull mode. (I/O CMOS, 1.8V or 3.3V) |
| G21 | SDIO_A_D1 | Digital | SDIO A Data lines. These signals operate in push-pull mode. (I/O CMOS, 1.8V or 3.3V) |
| G32 | eDP_B_HPD | Digital | Detection of Hot Plug / Unplug of secondary eDP display and notification of the link layer. (I CMOS, 1.8V, PU/PD: PD 1M, Module must tolerate high level in stand-by mode) |
| G33 | eDP_B_AUX_P | Digital | Secondary bidirectional eDP channel used for link management and device control (I/O LVDS DP, PD 100k, PU/PD: AC coupled off module) |
| G34 | GND | Ground | Module Signal and power return and GND reference (P) |
| G35 | eDP_B_LANE2_P | Digital | Secondary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module) |
| H1 | ETH_B_(R)(G)MII_TX_CLK | Digital | Transmit clock port B (I/O CMOS, 1.8V/2.5V/3.3V) |
| H2 | GND | Ground | Module Signal and power return and GND reference (P) |
| H3 | RGB_CS# | Digital | Chip select (O CMOS, 3.3V) |
| H4 | GND | Ground | Module Signal and power return and GND reference (P) |
| H15 | ETH_A_(S)(R)(G)MII_TXD0 | Digital | Transmit data bit 0 (transmitted first) port A (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _P when used as differential) |
| H16 | ETH_A_(S)(R)(G)MII_TXD2 | Digital | Transmit data bit 2 port A (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _P when used as differential) |
| H17 | GPIO_A_4 | Digital | General purpose I/O Contact A4 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| H18 | PWM_3 | Digital | Pulse width modulation 3 (O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| H19 | GPIO_B_4 | Digital | General purpose I/O Contact B4 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| H20 | SDIO_A_D2 | Digital | SDIO A Data lines. These signals operate in push-pull mode. (I/O CMOS, 1.8V or 3.3V) |
| H21 | SDIO_A_D3 | Digital | SDIO A Data lines. These signals operate in push-pull mode. (I/O CMOS, 1.8V or 3.3V) |
| H32 | GND | Ground | Module Signal and power return and GND reference (P) |
| H33 | eDP_B_AUX_N | Digital | Secondary bidirectional eDP channel used for link management and device control (I/O LVDS DP, PD 100k, PU/PD: AC coupled off module) |
| H34 | eDP_B_LANE3_P | Digital | Secondary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module) |
| H35 | eDP_B_LANE2_N | Digital | Secondary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module) |
| J1 | ETH_B_(S)(R)(G)MII_RXD0 | Digital | Receive data bit 0 (received first) port B (I CMOS, 1.8V/2.5V/3.3V, PU/PD: _P when used as differential) |
| J2 | ETH_B_(R)(G)MII_TX_EN(_ER) | Digital | Transmit enable (Error) port B (O CMOS, 1.8V/2.5V/3.3V) |
| J3 | RGB_RESET# | Digital | Global Reset (O CMOS, 3.3V) |
| J4 | RGB_DE | Digital | Data Enable (O CMOS, 3.3V) |
| J15 | ETH_A_(R)(G)MII_TX_CLK | Digital | Transmit clock port A (I/O CMOS, 1.8V/2.5V/3.3V) |
| J16 | GND | Ground | Module Signal and power return and GND reference (P) |
| J17 | GPIO_A_5 | Digital | General purpose I/O Contact A5 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| J18 | PWM_4 | Digital | Pulse width modulation 4 (O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| J19 | GPIO_B_5 | Digital | General purpose I/O Contact B5 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| J20 | GND | Ground | Module Signal and power return and GND reference (P) |
| J21 | SDIO_A_CD# | Digital | SDIO A Card Detect. This signal indicates when a SDIO/MMC card is present. (I OD CMOS, 1.8V or 3.3V, PU/PD: PU 10k) |
| J32 | CSI_B_CLOCK_N | Digital | CSI differential clock input (point to point) (I LVDS D-PHY) |
| J33 | GND | Ground | Module Signal and power return and GND reference (P) |
| J34 | eDP_B_LANE3_N | Digital | Secondary 4-lane eDP differential pair data lines (O LVDS DP, AC coupled off module) |
| J35 | GND | Ground | Module Signal and power return and GND reference (P) |
| K1 | ETH_B_(S)(R)(G)MII_RXD1 | Digital | Receive data bit 1 port B (I CMOS, 1.8V/2.5V/3.3V, PU/PD: _N when used as differential) |
| K2 | ETH_B_(R)(G)MII_RX_ER | Digital | Receive error port B (I CMOS, 1.8V/2.5V/3.3V) |
| K3 | RGB_HSYNC | Digital | horizontal synch (O CMOS, 3.3V) |
| K4 | RGB_DISP | Digital | Display ON/OFF (O CMOS, 3.3V) |
| K15 | ETH_A_(S)(R)(G)MII_RXD0 | Digital | Receive data bit 0 (received first) port A (I CMOS, 1.8V/2.5V/3.3V, PU/PD: _P when used as differential) |
| K16 | ETH_A_(R)(G)MII_TX_EN(_ER) | Digital | Transmit enable (Error) port A (O CMOS, 1.8V/2.5V/3.3V) |
| K17 | GPIO_A_6/ SPI_A_CS1# | Digital | General purpose I/O Contact A6 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V, Dual function: SPI_A_CS1#) |
| K18 | PWM_5 | Digital | Pulse width modulation 5 (O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| K19 | GPIO_B_6 | Digital | General purpose I/O Contact B6 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| K20 | SDIO_B_CLK | Digital | SDIO B Clock. With each cycle of this signal a one-bit transfer on the command and each data line occurs. (O CMOS, 1.8V or 3.3V) |
| K21 | SDIO_B_CMD | Digital | SDIO B Command/Response. This signal is used for card initialization and for command transfers. During initialization mode (I/O CMOS, 1.8V or 3.3V) |
| K32 | GND | Ground | Module Signal and power return and GND reference (P) |
| K33 | CSI_B_CLOCK_P | Digital | CSI differential clock input (point to point) (I LVDS D-PHY) |
| K34 | GND | Ground | Module Signal and power return and GND reference (P) |
| K35 | PCIe_B_HSO0_P | Digital | Differential PCIe link B transmit data pair (O LVDS PCIE, AC coupled off module) |
| L1 | ETH_B_(R)(G)MII_RX_DV(_ER) | Digital | Receive data valid (Error) port B (I CMOS, 1.8V/2.5V/3.3V) |
| L2 | GND | Ground | Module Signal and power return and GND reference (P) |
| L3 | RGB_VSYNC | Digital | Vertical synch (O CMOS, 3.3V) |
| L4 | GND | Ground | Module Signal and power return and GND reference (P) |
| L15 | ETH_A_(S)(R)(G)MII_RXD1 | Digital | Receive data bit 1 port A (I CMOS, 1.8V/2.5V/3.3V, PU/PD: _N when used as differential) |
| L16 | ETH_A_(R)(G)MII_RX_ER | Digital | Receive error port A (I CMOS, 1.8V/2.5V/3.3V) |
| L17 | GPIO_A_7/ SPI_B_CS1# | Digital | General purpose I/O Contact A7 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V, Dual function: SPI_B_CS1#) |
| L18 | GND | Ground | Module Signal and power return and GND reference (P) |
| L19 | GPIO_B_7 | Digital | General purpose I/O Contact B7 (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| L20 | SDIO_B_D0 | Digital | SDIO B Data lines. These signals operate in push-pull mode. (I/O CMOS, 1.8V or 3.3V) |
| L21 | SDIO_B_D1 | Digital | SDIO B Data lines. These signals operate in push-pull mode. (I/O CMOS, 1.8V or 3.3V) |
| L32 | CSI_B_DATA0_N | Digital | CSI differential input (point to point) (I LVDS D-PHY/ I LVDS M-PHY) |
| L33 | PCIe_B_PERST# | Digital | PCIe Port B reset output (O CMOS, 1.8V) |
| L34 | PCIe_B_HSI0_P | Digital | Differential PCIe link B receive data pair (I LVDS PCIE, AC coupled off module) |
| L35 | PCIe_B_HSO0_N | Digital | Differential PCIe link B transmit data pair (O LVDS PCIE, AC coupled off module) |
| M1 | ETH_B_(R)(G)MII_RXD2 | Digital | Receive data bit 2 port B (I CMOS, 1.8V/2.5V/3.3V) |
| M2 | ETH_B_SDP | Digital | Ethernet port B System Defined Contact (I/O CMOS, 1.8V/2.5V/3.3V) |
| M3 | RGB_B5 | Digital | Blue data bit 5 (O CMOS, 3.3V) |
| M4 | RGB_(PIXEL)CLK | Digital | Pixel clock signal (O CMOS, 3.3V) |
| M15 | ETH_A_(R)(G)MII_RX_DV(_ER) | Digital | Receive data valid port A (I CMOS, 1.8V/2.5V/3.3V) |
| M16 | GND | Ground | Module Signal and power return and GND reference (P) |
| M17 | ETH_IOPWR | Power | ETH voltage. It is used to provide the IO Voltage Level for all Ethernet interfaces. (PO, 1.8V/2.5V/3.3V, PU/PD: Minimum current: 100mA) |
| M18 | ADC_0 | Analog | Analog Digital Converter 0 (Analog, 0V – 1.8V) |
| M19 | VCC_2_TEST | Power | Module power voltage testpoint (PO) |
| M20 | GND | Ground | Module Signal and power return and GND reference (P) |
| M21 | SDIO_B_D2 | Digital | SDIO B Data lines. These signals operate in push-pull mode. (I/O CMOS, 1.8V or 3.3V) |
| M32 | GND | Ground | Module Signal and power return and GND reference (P) |
| M33 | CSI_B_DATA0_P | Digital | CSI differential input (point to point) (I LVDS D-PHY / I LVDS M-PHY) |
| M34 | PCIe_B_HSI0_N | Digital | Differential PCIe link B receive data pair (I LVDS PCIE, AC coupled off module) |
| M35 | GND | Ground | Module Signal and power return and GND reference (P) |
| N1 | ETH_B_(R)(G)MII_RXD3 | Digital | Receive data bit 3 port B (I CMOS, 1.8V/2.5V/3.3V) |
| N2 | RESERVED | NC | Reserved for future use (NC) |
| N3 | RGB_B3 | Digital | Blue data bit 3 (O CMOS, 3.3V) |
| N4 | RGB_B4 | Digital | Blue data bit 4 (O CMOS, 3.3V) |
| N15 | ETH_A_(R)(G)MII_RXD2 | Digital | Receive data bit 2 port A (I CMOS, 1.8V/2.5V/3.3V) |
| N16 | ETH_A_SDP | Digital | Ethernet port A System Defined Contact (I/O CMOS, 1.8V/2.5V/3.3V) |
| N17 | JTAG_TCK(SWCLK) | Digital | Test Clock (I CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| N18 | ADC_1 | Analog | Analog Digital Converter 1 (Analog, 0V – 1.8V) |
| N19 | JTAG_TMS(SWDIO) | Digital | Test Mode Select (I CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| N20 | SDIO_B_D3 | Digital | SDIO B Data lines. These signals operate in push-pull mode. (I/O CMOS, 1.8V or 3.3V) |
| N21 | SDIO_B_D4 | Digital | SDIO B Data lines. These signals operate in push-pull mode. (I/O CMOS, 1.8V or 3.3V) |
| N32 | CSI_B_DATA1_N | Digital | CSI differential input (point to point) (I LVDS D-PHY / I LVDS M-PHY) |
| N33 | ETH_CDE_MDC | Digital | Management bus clock signal for Ethernet C/D/E (O CMOS, 1.8V/2.5V/3.3V, PU/PD: Optional use) |
| N34 | GND | Ground | Module Signal and power return and GND reference (P) |
| N35 | ETH_C_(R)(G)MII_TX_CLK | Digital | Transmit clock port C (I/O CMOS, 1.8V/2.5V/3.3V) |
| P1 | ETH_B_(R)(G)MII_RX_CLK | Digital | Receive clock port B (I/O CMOS, 1.8V/2.5V/3.3V) |
| P2 | GND | Ground | Module Signal and power return and GND reference (P) |
| P3 | RGB_B2 | Digital | Blue data bit 2 (O CMOS, 3.3V) |
| P4 | GND | Ground | Module Signal and power return and GND reference (P) |
| P15 | ETH_A_(R)(G)MII_RXD3 | Digital | Receive data bit 3 port A (I CMOS, 1.8V/2.5V/3.3V) |
| P16 | Vendor Defined | Digital | Defined by module manufacturer |
| P17 | JTAG_TDI | Digital | Test Data Input (I CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| P18 | GND | Ground | Module Signal and power return and GND reference (P) |
| P19 | JTAG_RTCK | Digital | Returned Test Clock (O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| P20 | SDIO_B_D5 | Digital | SDIO B Data lines. These signals operate in push-pull mode. (I/O CMOS, 1.8V or 3.3V) |
| P21 | SDIO_B_D6 | Digital | SDIO B Data lines. These signals operate in push-pull mode. (I/O CMOS, 1.8V or 3.3V) |
| P32 | CSI_B_DATA1_P | Digital | CSI differential input (point to point) (I LVDS D-PHY / I LVDS M-PHY) |
| P33 | ETH_CDE_MDIO | Digital | Management bus data signal for Ethernet C/D/E (I/O CMOS, 1.8V/2.5V/3.3V, PU/PD: Optional use) |
| P34 | CSI_B_DATA2_N | Digital | CSI differential input (point to point) (I LVDS D-PHY / I LVDS M-PHY) |
| P35 | ETH_C_(R)(G)MII_RXD3 | Digital | Receive data bit 3 port C (I CMOS, 1.8V/2.5V/3.3V) |
| R1 | GND | Ground | Module Signal and power return and GND reference (P) |
| R2 | PCIe_SM_ALERT# | Digital | SMBus Alert# (interrupt) signal (I OD CMOS, 1.8V, PU/PD: PU 2k2) |
| R3 | RGB_B1 | Digital | Blue data bit 1 (O CMOS, 3.3V) |
| R4 | RGB_B0 | Digital | Blue data bit 0 (O CMOS, 3.3V) |
| R15 | ETH_A_(R)(G)MII_RX_CLK | Digital | Receive clock port A (I/O CMOS, 1.8V/2.5V/3.3V) |
| R16 | GND | Ground | Module Signal and power return and GND reference (P) |
| R17 | JTAG_TDO(SWO) | Digital | Test Data Output (O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| R18 | BOOT_SEL1# | Digital | I OD CMOS (1.8V, PU 10k, PU/PD: The boot medium is the choice of the module vendor.) |
| R19 | JTAG_nTRST | Digital | Test Reset, Active Low (I CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| R20 | GND | Ground | Module Signal and power return and GND reference (P) |
| R21 | SDIO_B_D7 | Digital | SDIO B Data lines. These signals operate in push-pull mode. (I/O CMOS, 1.8V or 3.3V) |
| R32 | GND | Ground | Module Signal and power return and GND reference (P) |
| R33 | CSI_B_DATA2_P | Digital | CSI differential input (point to point) (I LVDS D-PHY / I LVDS M-PHY) |
| R34 | ETH_C_SDP | Digital | Ethernet port C System Defined Contact (I/O CMOS, 1.8V/2.5V/3.3V) |
| R35 | ETH_C_(R)(G)MII_RXD2 | Digital | Receive data bit 2 port C (I CMOS, 1.8V/2.5V/3.3V) |
| T1 | PCIe_SMCLK | Digital | System management I2C bus CLK (O OD CMOS, 1.8V, PU/PD: PU 2k2) |
| T2 | PCIe_WAKE# | Digital | PCIe wake up interrupt to host – common to PCIe links A, B, C, D (I OD CMOS, 1.8V, PU/PD: PU 10k) |
| T3 | RGB_G4 | Digital | Green data bit 4 (O CMOS, 3.3V) |
| T4 | RGB_G5 | Digital | Green data bit 5 (O CMOS, 3.3V) |
| T15 | ETH_MDIO | Digital | Management bus data signal for Ethernet (I/O CMOS, 1.8V/2.5V/3.3V, PU/PD: Can be used for all ETH ports or for A exclusively) |
| T16 | ETH_MDC | Digital | Management bus clock signal for Ethernet (O CMOS, 1.8V/2.5V/3.3V, PU/PD: Can be used for all ETH ports or for A exclusively) |
| T17 | FORCE_RECOVERY# | Digital | If low on carrier board module enters recovery mode. (I OD CMOS, 1.8V, PU/PD: PU 10k, The recovery mode should be specified by module vendor.) |
| T18 | I2S_B_LRCLK | Digital | I2S Left & Right synchronization clock (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V, Module Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode) |
| T19 | I2S_B_BITCLK | Digital | I2S Digital audio clock (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V, Module Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode) |
| T20 | SDIO_B_IOPWR | Power | SDIO B Voltage. It is used to provide the IO Voltage Level (PO, 1.8V or 3.3V, PU/PD: Minimum current: 100mA) |
| T21 | SDIO_B_CD# | Digital | SDIO B Card Detect. This signal indicates when a SDIO/MMC card is present. (I OD CMOS, 1.8V or 3.3V, PU/PD: PU 10k) |
| T32 | CSI_B_DATA3_N | Digital | CSI differential input (point to point) (I LVDS D-PHY / I LVDS M-PHY) |
| T33 | CSI_B_DATA3_P | Digital | CSI differential input (point to point) (I LVDS D-PHY / I LVDS M-PHY) |
| T34 | GND | Ground | Module Signal and power return and GND reference (P) |
| T35 | ETH_C_(R)(G)MII_RX_DV(_ER) | Digital | Receive data valid (Error) port C (I CMOS, 1.8V/2.5V/3.3V) |
| U1 | PCIe_SMDAT | Digital | System management I2C bus DATA (I/O OD CMOS, 1.8V, PU/PD: PU 2k2) |
| U2 | GND | Ground | Module Signal and power return and GND reference (P) |
| U3 | RGB_G3 | Digital | Green data bit 3 (O CMOS, 3.3V) |
| U4 | GND | Ground | Module Signal and power return and GND reference (P) |
| U15 | SPI_A_SDI_(IO1) | Digital | SPI_A_SDI_(IO1) |
| U16 | SPI_A_SCK | Digital | SPI A Serial Data Clock (O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| U17 | RESET_IN# | Digital | Reset input from Carrier board. Carrier drives low to force a Module reset, floats the line otherwise. (I OD CMOS, 1.8V, PU/PD: PU 10K) |
| U18 | VCC_OUT_IO | Power | Provides IO voltage level for several interfaces to connect (PO, 1.8V/3.3V, PU/PD: 1.8V/3.3V on size 0, 1.8V on all other sizes – minimum current: 100 mA) |
| U19 | BOOT_SEL0# | Digital | I OD CMOS (1.8V, PU 10k, PU/PD: The boot medium is the choice of the module vendor.) |
| U20 | SDIO_B_WP | Digital | SDIO B Write Protect. This signal denotes the state of the write- protect tab on SD cards. (I OD CMOS, 1.8V or 3.3V, PU/PD: PU 10k, Tie to GND on carrier, if not used) |
| U21 | SDIO_B_PWR_EN | Digital | SDIO B Power Enable. This signal is used to enable the power being supplied to a SD/MMC card device. (O CMOS, 1.8V or 3.3V) |
| U32 | GPIO_D_0 | Digital | General purpose I/O Contact D0 (I/O CMOS, 1.8V) |
| U33 | GPIO_D_1 | Digital | General purpose I/O Contact D1 (I/O CMOS, 1.8V) |
| U34 | ETH_C_(R)(G)MII_RX_ER | Digital | Receive error port C (I CMOS, 1.8V/2.5V/3.3V) |
| U35 | ETH_C_(S)(R)(G)MII_RXD1 | Digital | Receive data bit 1 port C (I CMOS, 1.8V/2.5V/3.3V, PU/PD: _N when used as differential) |
| V1 | GND | Ground | Module Signal and power return and GND reference (P) |
| V2 | PCIe_A_PERST# | Digital | PCIe Port A reset output (O CMOS, 1.8V) |
| V3 | RGB_G1 | Digital | Green data bit 1 (O CMOS, 3.3V) |
| V4 | RGB_G2 | Digital | Green data bit 2 (O CMOS, 3.3V) |
| V15 | SPI_A_SDO_(IO0) | Digital | SPI_A_SDO_(IO0) |
| V16 | GND | Ground | Module Signal and power return and GND reference (P) |
| V17 | CARRIER_PWR_EN | Digital | Carrier board circuits should not be powered up until the module asserts the CARRIER_PWR_EN signal (O CMOS, 1.8V) |
| V18 | I2S_MCLK | Digital | Master clock output to I2S codec(s) (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| V19 | I2S_B_DATA_IN | Digital | I2S B Digital audio Input (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| V20 | GND | Ground | Module Signal and power return and GND reference (P) |
| V21 | I2S_A_DATA_IN | Digital | I2S A Digital audio Input (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| V32 | GPIO_D_2 | Digital | General purpose I/O Contact D2 (I/O CMOS, 1.8V) |
| V33 | GPIO_D_3 | Digital | General purpose I/O Contact D3 (I/O CMOS, 1.8V) |
| V34 | ETH_C_(R)(G)MII_TX_EN(_ER) | Digital | Transmit enable (Error) port C (O CMOS, 1.8V/2.5V/3.3V) |
| V35 | ETH_C_(S)(R)(G)MII_RXD0 | Digital | Receive data bit 0 (received first) port C (I CMOS, 1.8V/2.5V/3.3V, PU/PD: _P when used as differential) |
| W1 | PCIe_REFCLK_P | Digital | Differential PCIe reference clock output (O LVDS PCIE) |
| W2 | PCIe_CLKREQ# | Digital | PCIe reference clock request (I OD CMOS, 1.8V, PU/PD: PU 10k) |
| W3 | GND | Ground | Module Signal and power return and GND reference (P) |
| W4 | RGB_G0 | Digital | Green data bit 0 (O CMOS, 3.3V) |
| W15 | SPI_A_HOLD_(IO3) | Digital | SPI_A_HOLD_(IO3) |
| W16 | SPI_A_WP_(IO2) | Digital | SPI_A_WP_(IO2) |
| W17 | RTC_PWR | Power | Low current RTC circuit backup power – 3.0V nominal. May be sourced from a Carrier based Lithium cell or Super Cap. (P, If RTC is implemented, Module Vendor should ensure proper function of RTC during active main supply if this pin is not used) |
| W18 | I2S_A_LRCLK | Digital | I2S Left & Right synchronization clock (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V, Module Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode) |
| W19 | I2S_B_DATA_OUT | Digital | I2S B Digital audio Output (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| W20 | I2S_A_BITCLK | Digital | I2S Digital audio clock (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V, Module Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode) |
| W21 | I2S_A_DATA_OUT | Digital | I2S A Digital audio Output (I/O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| W32 | GPIO_D_4 | Digital | General purpose I/O Contact D4 (I/O CMOS, 1.8V) |
| W33 | GPIO_D_5 | Digital | General purpose I/O Contact D5 (I/O CMOS, 1.8V) |
| W34 | GND | Ground | Module Signal and power return and GND reference (P) |
| W35 | ETH_C_(R)(G)MII_RX_CLK | Digital | Receive clock port C (I/O CMOS, 1.8V/2.5V/3.3V) |
| Y1 | PCIe_REFCLK_N | Digital | Differential PCIe reference clock output (O LVDS PCIE) |
| Y2 | GND | Ground | Module Signal and power return and GND reference (P) |
| Y3 | VCC_5_TEST | Power | Module power voltage test point (PO) |
| Y4 | RGB_R5 | Digital | Red data bit 5 (O CMOS, 3.3V) |
| Y5 | RGB_R4 | Digital | Red data bit 4 (O CMOS, 3.3V) |
| Y6 | RGB_R2 | Digital | Red data bit 2 (O CMOS, 3.3V) |
| Y7 | RGB_R0 | Digital | Red data bit 0 (O CMOS, 3.3V) |
| Y8 | VCC_IN_5V | Power | Module power input voltage of 5V (P, Tolerance: 5V +-5%) |
| Y9 | VCC_IN_5V | Power | Module power input voltage of 5V (P, Tolerance: 5V +-5%) |
| Y10 | VCC_IN_5V | Power | Module power input voltage of 5V (P, Tolerance: 5V +-5%) |
| Y11 | VCC_IN_5V | Power | Module power input voltage of 5V (P, Tolerance: 5V +-5%) |
| Y13 | CARRIER_STBY# | Digital | The Module shall drive this signal low when the system is in a standby power state (O CMOS, 1.8V, PU/PD: Optional) |
| Y14 | RESET_OUT# | Digital | Reset output from CPU to reset peripherals on Carrier. (O CMOS, 1.8V) |
| Y15 | SPI_A_CS0# | Digital | SPI A Master Chip Select 0 (O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| Y16 | VCC_3_TEST | Power | Module power voltage testpoint (PO) |
| Y17 | VCC_IN_5V | Power | Module power input voltage of 5V – Primary voltage rail for size S, M and L modules (P, Tolerance: 5V +-5%) |
| Y18 | GND | Ground | Module Signal and power return and GND reference (P) |
| Y19 | VCC_IN_3V3 | Power | Module power input voltage of 3.3V – Primary voltage rail for 0 size modules (P, Tolerance: 3.3V +- 5%) |
| Y20 | VCC_4_TEST | Power | Module power voltage testpoint (PO) |
| Y21 | SPI_B_SCK | Digital | SPI B Serial Data Clock (O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| Y22 | SPI_B_SDI | Digital | SPI B Serial Data Input (I CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| Y23 | SPI_B_SDO | Digital | SPI B Serial Data Output (O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| Y25 | VCC_IN_5V | Power | Module power input voltage of 5V (P, Tolerance: 5V +-5%) |
| Y26 | VCC_IN_5V | Power | Module power input voltage of 5V (P, Tolerance: 5V +-5%) |
| Y27 | VCC_IN_5V | Power | Module power input voltage of 5V (P, Tolerance: 5V +-5%) |
| Y28 | VCC_IN_5V | Power | Module power input voltage of 5V (P, Tolerance: 5V +-5%) |
| Y29 | Vendor Defined | Digital | Defined by module manufacturer |
| Y30 | Vendor Defined | Digital | Defined by module manufacturer |
| Y31 | Vendor Defined | Digital | Defined by module manufacturer |
| Y32 | GPIO_D_6 | Digital | General purpose I/O Contact D6 (I/O CMOS, 1.8V) |
| Y33 | GPIO_D_7/ SPI_C_CS1# | Digital | General purpose I/O Contact D7 (I/O CMOS, 1.8V, PU/PD: Dual function: SPI_C_CS1#) |
| Y34 | ETH_C_(S)(R)(G)MII_TXD2 | Digital | Transmit data bit 2 port C (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _P when used as differential) |
| Y35 | ETH_C_(S)(R)(G)MII_TXD0 | Digital | Transmit data bit 0 (transmitted first) port C (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _P when used as differential) |
| AA1 | GND | Ground | Module Signal and power return and GND reference (P) |
| AA2 | RESERVED | NC | Reserved for future use (NC) |
| AA3 | DSI_TE | Digital | DSI panel tearing effect signal (I CMOS, 1.8V, PU/PD: not used in LVDS mode) |
| AA4 | GND | Ground | Module Signal and power return and GND reference (P) |
| AA5 | RGB_R3 | Digital | Red data bit 3 (O CMOS, 3.3V) |
| AA6 | RGB_R1 | Digital | Red data bit 1 (O CMOS, 3.3V) |
| AA7 | GND | Ground | Module Signal and power return and GND reference (P) |
| AA8 | GND | Ground | Module Signal and power return and GND reference (P) |
| AA9 | PWR_BTN# | Digital | Power-button input from Carrier board. Carrier to float the line in in-active state. Active low, level sensitive. Should be de-bounced on the Module. (I OD CMOS, 1.8 to 5V, PU/PD: PU 10K) |
| AA10 | GND | Ground | Module Signal and power return and GND reference (P) |
| AA11 | GND | Ground | Module Signal and power return and GND reference (P) |
| AA13 | RESERVED | NC | Reserved for future use (NC) |
| AA14 | GND | Ground | Module Signal and power return and GND reference (P) |
| AA15 | I2C_A_SCL | Digital | I2C Port A Clock Signal (I/O OD CMOS, VCC_OUT_IO, PU/PD: 1.8V, PU 2k2) |
| AA16 | I2C_A_SDA | Digital | I2C Port A Data Signal (I/O OD CMOS, VCC_OUT_IO, PU/PD: 1.8V, PU 2k2) |
| AA17 | GND | Ground | Module Signal and power return and GND reference (P) |
| AA18 | V_BAT | Power | Module power input battery voltage (P) |
| AA19 | GND | Ground | Module Signal and power return and GND reference (P) |
| AA20 | I2C_B_SCL | Digital | I2C Port B Clock Signal (I/O OD CMOS, VCC_OUT_IO, PU/PD: 1.8V, PU 2k2) |
| AA21 | I2C_B_SDA | Digital | I2C Port B Data Signal (I/O OD CMOS, VCC_OUT_IO, PU/PD: 1.8V, PU 2k2) |
| AA22 | GND | Ground | Module Signal and power return and GND reference (P) |
| AA23 | SPI_B_CS0# | Digital | SPI B Master Chip Select 0 (O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| AA25 | GND | Ground | Module Signal and power return and GND reference (P) |
| AA26 | GND | Ground | Module Signal and power return and GND reference (P) |
| AA27 | GND | Ground | Module Signal and power return and GND reference (P) |
| AA28 | GND | Ground | Module Signal and power return and GND reference (P) |
| AA29 | Vendor Defined | Digital | Defined by module manufacturer |
| AA30 | Vendor Defined | Digital | Defined by module manufacturer |
| AA31 | Vendor Defined | Digital | Defined by module manufacturer |
| AA32 | GND | Ground | Module Signal and power return and GND reference (P) |
| AA33 | VCC_7_TEST | Power | Module power voltage testpoint (PO) |
| AA34 | ETH_C_(S)(R)(G)MII_TXD3 | Digital | Transmit data bit 3 port C (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _N when used as differential) |
| AA35 | ETH_C_(S)(R)(G)MII_TXD1 | Digital | Transmit data bit 1 port C (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _N when used as differential) |
| AB1 | PCIe_A_HSI0_P | Digital | Differential PCIe link A receive data pair (I LVDS PCIE, AC coupled off module) |
| AB2 | PCIe_A_HSI0_N | Digital | Differential PCIe link A receive data pair (I LVDS PCIE, AC coupled off module) |
| AB3 | GND | Ground | Module Signal and power return and GND reference (P) |
| AB4 | DSI_DATA3_P/ LVDS_A_LANE3_P | Digital | DSI differential output (point to point) / LVDS channel A differential pair data lines (O LVDS D-PHY / O LVDS LCD, Alternate use: LVDS_A_ LANE3_P) |
| AB5 | DSI_DATA3_N/ LVDS_A_LANE3_N | Digital | DSI differential output (point to point) / LVDS channel A differential pair data lines (O LVDS D-PHY / O LVDS LCD, Alternate use: LVDS_A_ LANE3_N) |
| AB6 | GND | Ground | Module Signal and power return and GND reference (P) |
| AB7 | DSI_CLOCK_P/ LVDS_A_CLK_P | Digital | DSI differential clock output (point to point) / LVDS channel A differential pair clock lines (O LVDS D-PHY / O LVDS LCD, Alternate use: LVDS_A_CLK_P) |
| AB8 | DSI_CLOCK_N/ LVDS_A_CLK_N | Digital | DSI differential clock output (point to point) / LVDS channel A differential pair clock lines (O LVDS D-PHY / O LVDS LCD, Alternate use: LVDS_A_CLK_N) |
| AB9 | GND | Ground | Module Signal and power return and GND reference (P) |
| AB10 | DSI_DATA0_P/ LVDS_A_LANE0_P | Digital | DSI differential output (point to point) / LVDS channel A differential pair data lines (O LVDS D-PHY / O LVDS LCD, Alternate use: LVDS_A_LANE0_P) |
| AB11 | DSI_DATA0_N/ LVDS_A_LANE0_N | Digital | DSI differential output (point to point) / LVDS channel A differential pair data lines (O LVDS D-PHY / O LVDS LCD, Alternate use: LVDS_A_LANE0_N) |
| AB13 | USB_A_D_N | Digital | USB differential data pairs for port A (I/O USB, USB) |
| AB14 | USB_A_ID | Digital | Input Contact to announce OTG device insertion on USB 2.0 port (I OD CMOS, 1.8V, PU/PD: PU 10k) |
| AB15 | GND | Ground | Module Signal and power return and GND reference (P) |
| AB16 | USB_A_VBUS | Digital | USB port 0 port power detection (I USB VBUS 5V, USB VBUS 5V) |
| AB17 | CAN_A_RX | Digital | CAN port A Receive input (I CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| AB18 | V_BAT | Power | Module power input battery voltage (P) |
| AB19 | CAN_B_RX | Digital | CAN port B Receive input (I CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| AB20 | USB_B_VBUS | Digital | USB port 0 port power detection (I USB VBUS 5V, USB VBUS 5V) |
| AB21 | GND | Ground | Module Signal and power return and GND reference (P) |
| AB22 | USB_B_ID | Digital | Input Contact to announce OTG device insertion on USB 2.0 port (I OD CMOS, 1.8V, PU/PD: PU 10k) |
| AB23 | USB_B_D_N | Digital | USB differential data pairs for port B (I/O USB, USB) |
| AB25 | CAM_B_SCL/ CSI_B_TX_P | Digital | I2C clock for serial camera data support link or differential data lane (I/O OD CMOS / O LVDS M-PHY, 1.8V, PU/PD: PU 2.2K, MIPI-CSI 2.0 mode uses CAM_B_SCL MIPI-CSI 3.0 mode uses CSI_B_TX_P) |
| AB26 | CAM_B_SDA/ CSI_B_TX_N | Digital | I2C data for serial camera data support link or differential data lane (I/O OD CMOS / O LVDS M-PHY, 1.8V, PU/PD: PU 2.2K, MIPI-CSI 2.0 mode uses CAM_B_SDA MIPI-CSI 3.0 mode uses CSI_B_TX_N) |
| AB27 | UFS_RESET# | Digital | UFS reset output (O CMOS, 1.8V / 1.2V, PU/PD: USF 3.0 need 1.2V I/O level) |
| AB28 | GND | Ground | Module Signal and power return and GND reference (P) |
| AB29 | UFS_TX1_P | Digital | UFS differential output (point to point) (O LVDS UFS) |
| AB30 | UFS_TX1_N | Digital | UFS differential output (point to point) (O LVDS UFS) |
| AB31 | GND | Ground | Module Signal and power return and GND reference (P) |
| AB32 | UFS_RX1_P | Digital | UFS differential input (point to point) (I LVDS UFS) |
| AB33 | UFS_RX1_N | Digital | UFS differential input (point to point) (I LVDS UFS) |
| AB34 | GND | Ground | Module Signal and power return and GND reference (P) |
| AB35 | ETH_C_(R)(G)MII_COL | Digital | Collision detect (half speed only) port C (I CMOS, 1.8V/2.5V/3.3V) |
| AC2 | PCIe_A_HSO0_P | Digital | Differential PCIe link A transmit data pair (O LVDS PCIE, AC coupled off module) |
| AC3 | PCIe_A_HSO0_N | Digital | Differential PCIe link A transmit data pair (O LVDS PCIE, AC coupled off module) |
| AC4 | GND | Ground | Module Signal and power return and GND reference (P) |
| AC5 | DSI_DATA2_P/ LVDS_A_LANE2_P | Digital | DSI differential output (point to point) / LVDS channel A differential pair data lines (O LVDS D-PHY / O LVDS LCD, Alternate use: LVDS_A_ LANE2_P) |
| AC6 | DSI_DATA2_N/ LVDS_A_LANE2_N | Digital | DSI differential output (point to point) / LVDS channel A differential pair data lines (O LVDS D-PHY / O LVDS LCD, Alternate use: LVDS_A_ LANE2_N) |
| AC7 | GND | Ground | Module Signal and power return and GND reference (P) |
| AC8 | DSI_DATA1_P/ LVDS_A_LANE1_P | Digital | DSI differential output (point to point) / LVDS channel A differential pair data lines (O LVDS D-PHY / O LVDS LCD, Alternate use: LVDS_A_ LANE1_P) |
| AC9 | DSI_DATA1_N/ LVDS_A_LANE1_N | Digital | DSI differential output (point to point) / LVDS channel A differential pair data lines (O LVDS D-PHY / O LVDS LCD, Alternate use: LVDS_A_ LANE1_N) |
| AC10 | GND | Ground | Module Signal and power return and GND reference (P) |
| AC14 | USB_A_D_P | Digital | USB differential data pairs for port A (I/O USB, USB) |
| AC15 | USB_A_OC# | Digital | USB over-current for port A (I OD CMOS, 1.8V, PU/PD: PU 10k) |
| AC16 | USB_A_EN | Digital | Power enable for USB VBUS voltage (O CMOS, 1.8V) |
| AC17 | CAN_A_TX | Digital | CAN port A Transmit output (O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| AC18 | DEBUG_EN | Digital | Enables JTAG function (I CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| AC19 | CAN_B_TX | Digital | CAN port B Transmit output (O CMOS, VCC_OUT_IO, PU/PD: 1.8V) |
| AC20 | USB_B_EN | Digital | Power enable for USB VBUS voltage (O CMOS, 1.8V) |
| AC21 | USB_B_OC# | Digital | USB over-current for port B (I OD CMOS, 1.8V, PU/PD: PU 10k) |
| AC22 | USB_B_D_P | Digital | USB differential data pairs for port B (I/O USB, USB) |
| AC26 | UFS_CLK | Digital | UFS reference clock output (O CMOS, 1.8V / 1.2 V, PU/PD: USF 3.0 need 1.2V I/O level) |
| AC27 | GND | Ground | Module Signal and power return and GND reference (P) |
| AC28 | UFS_TX0_P | Digital | UFS differential output (point to point) (O LVDS UFS) |
| AC29 | UFS_TX0_N | Digital | UFS differential output (point to point) (O LVDS UFS) |
| AC30 | GND | Ground | Module Signal and power return and GND reference (P) |
| AC31 | UFS_RX0_P | Digital | UFS differential input (point to point) (I LVDS UFS) |
| AC32 | UFS_RX0_N | Digital | UFS differential input (point to point) (I LVDS UFS) |
| AC33 | GND | Ground | Module Signal and power return and GND reference (P) |
| AC34 | ETH_C_(R)(G)MII_CRS | Digital | Carrier Sense port C (I CMOS, 1.8V/2.5V/3.3V) |
| AE2 | GND | Ground | Module Signal and power return and GND reference (P) |
| AE3 | ETH_D_(R)(G)MII_CRS | Digital | Carrier Sense port D (I CMOS, 1.8V/2.5V/3.3V) |
| AE4 | VCC_IN_5V | Power | Module power input voltage of 5V (P, Tolerance: 5V +-5%) |
| AE32 | RESERVED | NC | Reserved for future use (NC) |
| AE33 | PCIe_C_PERST# | Digital | PCIe Port C reset output (O CMOS, 1.8V) |
| AE34 | GND | Ground | Module Signal and power return and GND reference (P) |
| AF1 | ETH_D_(S)(R)(G)MII_TXD0 | Digital | Transmit data bit 0 (transmitted first) port D (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _P when used as differential) |
| AF2 | ETH_D_(S)(R)(G)MII_TXD3 | Digital | Transmit data bit 3 port D (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _N when used as differential) |
| AF3 | ETH_D_(R)(G)MII_COL | Digital | Collision detect (half speed only) port D (I CMOS, 1.8V/2.5V/3.3V) |
| AF4 | VCC_IN_5V | Power | Module power input voltage of 5V (P, Tolerance: 5V +-5%) |
| AF32 | GPIO_E_0 | Digital | General purpose I/O Contact E0 (I/O CMOS, 1.8V) |
| AF33 | GPIO_E_1 | Digital | General purpose I/O Contact E1 (I/O CMOS, 1.8V) |
| AF34 | PCIe_C_HSO3_P | Digital | Differential PCIe link C transmit data pair (O LVDS PCIE, AC coupled off module) |
| AF35 | GND | Ground | Module Signal and power return and GND reference (P) |
| AG1 | ETH_D_(S)(R)(G)MII_TXD1 | Digital | Transmit data bit 1 port D (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _N when used as differential) |
| AG2 | ETH_D_(S)(R)(G)MII_TXD2 | Digital | Transmit data bit 2 port D (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _P when used as differential) |
| AG3 | GND | Ground | Module Signal and power return and GND reference (P) |
| AG4 | VCC_IN_5V | Power | Module power input voltage of 5V (P, Tolerance: 5V +-5%) |
| AG32 | GPIO_E_2 | Digital | General purpose I/O Contact E2 (I/O CMOS, 1.8V) |
| AG33 | GPIO_E_3 | Digital | General purpose I/O Contact E3 (I/O CMOS, 1.8V) |
| AG34 | PCIe_C_HSO3_N | Digital | Differential PCIe link C transmit data pair (O LVDS PCIE, AC coupled off module) |
| AG35 | PCIe_C_HSI3_P | Digital | Differential PCIe link C receive data pair (I LVDS PCIE, AC coupled off module) |
| AH1 | ETH_D_(R)(G)MII_TX_CLK | Digital | Transmit clock port D (I/O CMOS, 1.8V/2.5V/3.3V) |
| AH2 | GND | Ground | Module Signal and power return and GND reference (P) |
| AH3 | VCC_IN_5V | Power | Module power input voltage of 5V (P, Tolerance: 5V +-5%) |
| AH4 | VCC_IN_5V | Power | Module power input voltage of 5V (P, Tolerance: 5V +-5%) |
| AH32 | GPIO_E_4 | Digital | General purpose I/O Contact E4 (I/O CMOS, 1.8V) |
| AH33 | GPIO_E_5 | Digital | General purpose I/O Contact E5 (I/O CMOS, 1.8V) |
| AH34 | GND | Ground | Module Signal and power return and GND reference (P) |
| AH35 | PCIe_C_HSI3_N | Digital | Differential PCIe link C receive data pair (I LVDS PCIE, AC coupled off module) |
| AJ1 | ETH_D_(S)(R)(G)MII_RXD0 | Digital | Receive data bit 0 (received first) port D (I CMOS, 1.8V/2.5V/3.3V, PU/PD: _P when used as differential) |
| AJ2 | ETH_D_(R)(G)MII_TX_EN(_ER) | Digital | Transmit enable (Error) port D (O CMOS, 1.8V/2.5V/3.3V) |
| AJ3 | VCC_IN_5V | Power | Module power input voltage of 5V (P, Tolerance: 5V +-5%) |
| AJ4 | VCC_IN_5V | Power | Module power input voltage of 5V (P, Tolerance: 5V +-5%) |
| AJ32 | GPIO_E_6 | Digital | General purpose I/O Contact E6 (I/O CMOS, 1.8V) |
| AJ33 | GPIO_E_7 | Digital | General purpose I/O Contact E7 (I/O CMOS, 1.8V) |
| AJ34 | PCIe_C_HSO2_P | Digital | Differential PCIe link C transmit data pair (O LVDS PCIE, AC coupled off module) |
| AJ35 | GND | Ground | Module Signal and power return and GND reference (P) |
| AK1 | ETH_D_(S)(R)(G)MII_RXD1 | Digital | Receive data bit 1 port D (I CMOS, 1.8V/2.5V/3.3V, PU/PD: _N when used as differential) |
| AK2 | ETH_D_(R)(G)MII_RX_ER | Digital | Receive error port D (I CMOS, 1.8V/2.5V/3.3V) |
| AK3 | GND | Ground | Module Signal and power return and GND reference (P) |
| AK4 | VCC_IN_5V | Power | Module power input voltage of 5V (P, Tolerance: 5V +-5%) |
| AK32 | Vendor Defined | Digital | Defined by module manufacturer |
| AK33 | Vendor Defined | Digital | Defined by module manufacturer |
| AK34 | PCIe_C_HSO2_N | Digital | Differential PCIe link C transmit data pair (O LVDS PCIE, AC coupled off module) |
| AK35 | PCIe_C_HSI2_P | Digital | Differential PCIe link C receive data pair (I LVDS PCIE, AC coupled off module) |
| AL1 | ETH_D_(R)(G)MII_RX_DV(_ER) | Digital | Receive data valid (Error) port D (I CMOS, 1.8V/2.5V/3.3V) |
| AL2 | GND | Ground | Module Signal and power return and GND reference (P) |
| AL3 | RESERVED | NC | Reserved for future use (NC) |
| AL4 | RESERVED | NC | Reserved for future use (NC) |
| AL32 | Vendor Defined | Digital | Defined by module manufacturer |
| AL33 | Vendor Defined | Digital | Defined by module manufacturer |
| AL34 | GND | Ground | Module Signal and power return and GND reference (P) |
| AL35 | PCIe_C_HSI2_N | Digital | Differential PCIe link C receive data pair (I LVDS PCIE, AC coupled off module) |
| AM1 | ETH_D_(R)(G)MII_RXD2 | Digital | Receive data bit 2 port D (I CMOS, 1.8V/2.5V/3.3V) |
| AM2 | ETH_D_SDP | Digital | Ethernet port D System Defined Contact (I/O CMOS, 1.8V/2.5V/3.3V) |
| AM3 | RESERVED | NC | Reserved for future use (NC) |
| AM4 | RESERVED | NC | Reserved for future use (NC) |
| AM5 | RESERVED | NC | Reserved for future use (NC) |
| AM6 | RESERVED | NC | Reserved for future use (NC) |
| AM7 | RESERVED | NC | Reserved for future use (NC) |
| AM8 | RESERVED | NC | Reserved for future use (NC) |
| AM9 | RESERVED | NC | Reserved for future use (NC) |
| AM10 | RESERVED | NC | Reserved for future use (NC) |
| AM11 | LVDS_I2C_CLK | Digital | DDC clock line used for flat panel detection and control (O OD CMOS, 1.8V, PU/PD: PU 2k2) |
| AM12 | LVDS_I2C_DAT | Digital | DDC data line used for flat panel detection and control (I/O OD CMOS, 1.8V, PU/PD: PU 2k2) |
| AM13 | GND | Ground | Module Signal and power return and GND reference (P) |
| AM14 | LVDS_B_LANE3_N | Digital | LVDS channel B differential pair data lines (O LVDS LCD) |
| AM15 | LVDS_B_LANE3_P | Digital | LVDS channel B differential pair data lines (O LVDS LCD) |
| AM16 | GND | Ground | Module Signal and power return and GND reference (P) |
| AM17 | LVDS_B_LANE2_N | Digital | LVDS channel B differential pair data lines (O LVDS LCD) |
| AM18 | LVDS_B_LANE2_P | Digital | LVDS channel B differential pair data lines (O LVDS LCD) |
| AM19 | GND | Ground | Module Signal and power return and GND reference (P) |
| AM20 | LVDS_B_LANE0_N | Digital | LVDS channel B differential pair data lines (O LVDS LCD) |
| AM21 | LVDS_B_LANE0_P | Digital | LVDS channel B differential pair data lines (O LVDS LCD) |
| AM22 | GND | Ground | Module Signal and power return and GND reference (P) |
| AM23 | RESERVED | NC | Reserved for future use (NC) |
| AM24 | RESERVED | NC | Reserved for future use (NC) |
| AM25 | RESERVED | NC | Reserved for future use (NC) |
| AM26 | RESERVED | NC | Reserved for future use (NC) |
| AM27 | RESERVED | NC | Reserved for future use (NC) |
| AM28 | RESERVED | NC | Reserved for future use (NC) |
| AM29 | RESERVED | NC | Reserved for future use (NC) |
| AM30 | RESERVED | NC | Reserved for future use (NC) |
| AM31 | RESERVED | NC | Reserved for future use (NC) |
| AM32 | Vendor Defined | Digital | Defined by module manufacturer |
| AM33 | Vendor Defined | Digital | Defined by module manufacturer |
| AM34 | PCIe_C_HSO1_P | Digital | Differential PCIe link C transmit data pair (O LVDS PCIE, AC coupled off module) |
| AM35 | GND | Ground | Module Signal and power return and GND reference (P) |
| AN1 | ETH_D_(R)(G)MII_RXD3 | Digital | Receive data bit 3 port D (I CMOS, 1.8V/2.5V/3.3V) |
| AN2 | RESERVED | NC | Reserved for future use (NC) |
| AN3 | GND | Ground | Module Signal and power return and GND reference (P) |
| AN4 | ETH_E_(R)(G)MII_CRS | Digital | Carrier Sense port E (I CMOS, 1.8V/2.5V/3.3V) |
| AN5 | RESERVED | NC | Reserved for future use (NC) |
| AN6 | GND | Ground | Module Signal and power return and GND reference (P) |
| AN7 | RESERVED | NC | Reserved for future use (NC) |
| AN8 | RESERVED | NC | Reserved for future use (NC) |
| AN9 | GND | Ground | Module Signal and power return and GND reference (P) |
| AN10 | ETH_E_(R)(G)MII_RX_CLK | Digital | Receive clock port E (I/O CMOS, 1.8V/2.5V/3.3V) |
| AN11 | GND | Ground | Module Signal and power return and GND reference (P) |
| AN12 | LVDS_A_CLK_N | Digital | LVDS channel A differential pair clock lines (O LVDS LCD) |
| AN13 | LVDS_A_CLK_P | Digital | LVDS channel A differential pair clock lines (O LVDS LCD) |
| AN14 | LVDS_VDD_EN | Digital | LVDS channel power enable, active high (O CMOS, 1.8V) |
| AN15 | GND | Ground | Module Signal and power return and GND reference (P) |
| AN16 | LVDS_B_CLK_N | Digital | LVDS channel B differential pair clock lines (O LVDS LCD) |
| AN17 | LVDS_B_CLK_P | Digital | LVDS channel B differential pair clock lines (O LVDS LCD) |
| AN18 | GND | Ground | Module Signal and power return and GND reference (P) |
| AN19 | LVDS_B_LANE1_N | Digital | LVDS channel B differential pair data lines (O LVDS LCD) |
| AN20 | LVDS_B_LANE1_P | Digital | LVDS channel B differential pair data lines (O LVDS LCD) |
| AN21 | GND | Ground | Module Signal and power return and GND reference (P) |
| AN22 | LVDS_BL_PWM | Digital | LVDS channel brightness control through pulse width modulation (O CMOS, 1.8V) |
| AN23 | LVDS_BL_EN | Digital | LVDS channel backlight enable, active high (O CMOS, 1.8V) |
| AN24 | RESERVED | NC | Reserved for future use (NC) |
| AN25 | RESERVED | NC | Reserved for future use (NC) |
| AN26 | RESERVED | NC | Reserved for future use (NC) |
| AN27 | RESERVED | NC | Reserved for future use (NC) |
| AN28 | RESERVED | NC | Reserved for future use (NC) |
| AN29 | RESERVED | NC | Reserved for future use (NC) |
| AN30 | RESERVED | NC | Reserved for future use (NC) |
| AN31 | RESERVED | NC | Reserved for future use (NC) |
| AN32 | PCIe_D_PERST# | Digital | PCIe Port D reset output (O CMOS, 1.8V) |
| AN33 | GND | Ground | Module Signal and power return and GND reference (P) |
| AN34 | PCIe_C_HSO1_N | Digital | Differential PCIe link C transmit data pair (O LVDS PCIE, AC coupled off module) |
| AN35 | PCIe_C_HSI1_P | Digital | Differential PCIe link C receive data pair (I LVDS PCIE, AC coupled off module) |
| AP1 | ETH_D_(R)(G)MII_RX_CLK | Digital | Receive clock port D (I/O CMOS, 1.8V/2.5V/3.3V) |
| AP2 | GND | Ground | Module Signal and power return and GND reference (P) |
| AP3 | ETH_E_(R)(G)MII_TXD2 | Digital | Transmit data bit 2 port E (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _P when used as differential) |
| AP4 | ETH_E_(R)(G)MII_TXD3 | Digital | Transmit data bit 3 port E (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _N when used as differential) |
| AP5 | GND | Ground | Module Signal and power return and GND reference (P) |
| AP6 | ETH_E_(R)(G)MII_TX_EN(_ER) | Digital | Transmit enable (Error) port E (O CMOS, 1.8V/2.5V/3.3V) |
| AP7 | ETH_E_(R)(G)MII_RX_ER | Digital | Receive error port E (I CMOS, 1.8V/2.5V/3.3V) |
| AP8 | GND | Ground | Module Signal and power return and GND reference (P) |
| AP9 | ETH_E_SDP | Digital | Ethernet port E System Defined Contact (I/O CMOS, 1.8V/2.5V/3.3V) |
| AP10 | RESERVED | NC | Reserved for future use (NC) |
| AP11 | LVDS_A_LANE3_N | Digital | LVDS channel A differential pair data lines (O LVDS LCD) |
| AP12 | LVDS_A_LANE3_P | Digital | LVDS channel A differential pair data lines (O LVDS LCD) |
| AP13 | GND | Ground | Module Signal and power return and GND reference (P) |
| AP14 | LVDS_A_LANE2_N | Digital | LVDS channel A differential pair data lines (O LVDS LCD) |
| AP15 | LVDS_A_LANE2_P | Digital | LVDS channel A differential pair data lines (O LVDS LCD) |
| AP16 | GND | Ground | Module Signal and power return and GND reference (P) |
| AP17 | LVDS_A_LANE0_N | Digital | LVDS channel A differential pair data lines (O LVDS LCD) |
| AP18 | LVDS_A_LANE0_P | Digital | LVDS channel A differential pair data lines (O LVDS LCD) |
| AP19 | GND | Ground | Module Signal and power return and GND reference (P) |
| AP20 | PCIe_D_HSO0_N | Digital | Differential PCIe link D transmit data pair (O LVDS PCIE, AC coupled off module) |
| AP21 | PCIe_D_HSO0_P | Digital | Differential PCIe link D transmit data pair (O LVDS PCIE, AC coupled off module) |
| AP22 | GND | Ground | Module Signal and power return and GND reference (P) |
| AP23 | PCIe_D_HSO1_N | Digital | Differential PCIe link D transmit data pair (O LVDS PCIE, AC coupled off module) |
| AP24 | PCIe_D_HSO1_P | Digital | Differential PCIe link D transmit data pair (O LVDS PCIE, AC coupled off module) |
| AP25 | GND | Ground | Module Signal and power return and GND reference (P) |
| AP26 | PCIe_D_HSI2_N | Digital | Differential PCIe link D receive data pair (I LVDS PCIE, AC coupled off module) |
| AP27 | PCIe_D_HSI2_P | Digital | Differential PCIe link D receive data pair (I LVDS PCIE, AC coupled off module) |
| AP28 | GND | Ground | Module Signal and power return and GND reference (P) |
| AP29 | PCIe_D_HSI3_N | Digital | Differential PCIe link D receive data pair (I LVDS PCIE, AC coupled off module) |
| AP30 | PCIe_D_HSI3_P | Digital | Differential PCIe link D receive data pair (I LVDS PCIE, AC coupled off module) |
| AP31 | GND | Ground | Module Signal and power return and GND reference (P) |
| AP32 | PCIe_C_HSI0_N | Digital | Differential PCIe link C receive data pair (I LVDS PCIE, AC coupled off module) |
| AP33 | PCIe_C_HSI0_P | Digital | Differential PCIe link C receive data pair (I LVDS PCIE, AC coupled off module) |
| AP34 | GND | Ground | Module Signal and power return and GND reference (P) |
| AP35 | PCIe_C_HSI1_N | Digital | Differential PCIe link C receive data pair (I LVDS PCIE, AC coupled off module) |
| AR2 | ETH_E_(R)(G)MII_COL | Digital | Collision detect (half speed only) port E (I CMOS, 1.8V/2.5V/3.3V) |
| AR3 | ETH_E_(S)(R)(G)MII_TXD0 | Digital | Transmit data bit 0 (transmitted first) port E (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _P when used as differential) |
| AR4 | ETH_E_(S)(R)(G)MII_TXD1 | Digital | Transmit data bit 1 port E (O CMOS, 1.8V/2.5V/3.3V, PU/PD: _N when used as differential) |
| AR5 | ETH_E_(R)(G)MII_TX_CLK | Digital | Transmit clock port E (I/O CMOS, 1.8V/2.5V/3.3V) |
| AR6 | ETH_E_(S)(R)(G)MII_RXD0 | Digital | Receive data bit 0 (received first) port E (I CMOS, 1.8V/2.5V/3.3V, PU/PD: _P when used as differential) |
| AR7 | ETH_E_(S)(R)(G)MII_RXD1 | Digital | Receive data bit 1 port E (I CMOS, 1.8V/2.5V/3.3V, PU/PD: _N when used as differential) |
| AR8 | ETH_E_(R)(G)MII_RX_DV(_ER) | Digital | Receive data valid (Error) port E (I CMOS, 1.8V/2.5V/3.3V) |
| AR9 | ETH_E_(R)(G)MII_RXD2 | Digital | Receive data bit 2 port E (I CMOS, 1.8V/2.5V/3.3V) |
| AR10 | ETH_E_(R)(G)MII_RXD3 | Digital | Receive data bit 3 port E (I CMOS, 1.8V/2.5V/3.3V) |
| AR14 | GND | Ground | Module Signal and power return and GND reference (P) |
| AR15 | LVDS_A_LANE1_N | Digital | LVDS channel A differential pair data lines (O LVDS LCD) |
| AR16 | LVDS_A_LANE1_P | Digital | LVDS channel A differential pair data lines (O LVDS LCD) |
| AR17 | GND | Ground | Module Signal and power return and GND reference (P) |
| AR18 | PCIe_D_HSI0_N | Digital | Differential PCIe link D receive data pair (I LVDS PCIE, AC coupled off module) |
| AR19 | PCIe_D_HSI0_P | Digital | Differential PCIe link D receive data pair (I LVDS PCIE, AC coupled off module) |
| AR20 | GND | Ground | Module Signal and power return and GND reference (P) |
| AR21 | PCIe_D_HSI1_N | Digital | Differential PCIe link D receive data pair (I LVDS PCIE, AC coupled off module) |
| AR22 | PCIe_D_HSI1_P | Digital | Differential PCIe link D receive data pair (I LVDS PCIE, AC coupled off module) |
| AR26 | GND | Ground | Module Signal and power return and GND reference (P) |
| AR27 | PCIe_D_HSO2_N | Digital | Differential PCIe link D transmit data pair (O LVDS PCIE, AC coupled off module) |
| AR28 | PCIe_D_HSO2_P | Digital | Differential PCIe link D transmit data pair (O LVDS PCIE, AC coupled off module) |
| AR29 | GND | Ground | Module Signal and power return and GND reference (P) |
| AR30 | PCIe_D_HSO3_N | Digital | Differential PCIe link D transmit data pair (O LVDS PCIE, AC coupled off module) |
| AR31 | PCIe_D_HSO3_P | Digital | Differential PCIe link D transmit data pair (O LVDS PCIE, AC coupled off module) |
| AR32 | GND | Ground | Module Signal and power return and GND reference (P) |
| AR33 | PCIe_C_HSO0_N | Digital | Differential PCIe link C transmit data pair (O LVDS PCIE, AC coupled off module) |
| AR34 | PCIe_C_HSO0_P | Digital | Differential PCIe link C transmit data pair (O LVDS PCIE, AC coupled off module) |