ISL78420 Tri-level PWM high/low-side MOSFET gate driver
Synchronous high/low-side NMOS gate driver with tri-level PWM input, adjustable dead time via RDT, bootstrap diode, and VDD/VHB undervoltage protection. -40 to +125C.
Aliase:ISL78420AVEZ, ISL78420AVEZ-T, ISL78420AVEZ-T7A
HTSSOP-14 Top View
15 Pins
Pin-Tabelle15
| Pin | Signal / Name | Typ | Alternative Funktionen |
|---|---|---|---|
| 1 | NC | NC | No connect, isolated from all other pins; may optionally tie to VSS |
| 2 | NC | NC | No connect, isolated from all other pins; may optionally tie to VSS |
| 3 | HB | Digital | High-side bootstrap supply for upper gate driver, referenced to HSBootstrap capacitor connection (with HS) |
| 4 | HO | Digital | High-side output driving gate of high-side NMOS |
| 5 | HS | Digital | High-side gate driver reference node, source of high-side NMOSBootstrap capacitor connection (with HB) |
| 6 | NC | NC | No connect, isolated from all other pins; may optionally tie to VSS |
| 7 | NC | NC | No connect, isolated from all other pins; may optionally tie to VSS |
| 8 | NC | NC | No connect, isolated from all other pins; may optionally tie to VSS |
| 9 | RDT | Analog | Dead-time resistor to VSS; sets LO-to-HO and HO-to-LO delay |
| 10 | EN | Digital | Output enable; low forces HO and LO low, internal 210k pull-down |
| 11 | PWM | Digital | Tri-level PWM input: high drives HO, low drives LO, mid-level turns both off |
| 12 | VSS | Ground | Analog supply ground, decouple to VDD with 4.7uF or larger |
| 13 | LO | Digital | Low-side output driving gate of low-side NMOS |
| 14 | VDD | Power | Analog input supply and positive supply for lower gate driverDecouple to VSS with 4.7uF or larger ceramic plus 0.1uF close to pins |
| EP | EPAD | NC | Exposed pad, electrically isolated; connect to VSS plane for heat removal |