74HC165 8-Bit Parallel-In / Serial-Out Shift Register
8-bit parallel-load shift register. Pull ~PL LOW to latch parallel inputs D0–D7; then clock out serially via Q7 (or its complement ~Q7). ~CE (clock enable, Active Low) gates the clock. Commonly chained for reading multiple buttons or sensors over SPI.
Aliase:SN74HC165N, 74HCT165, PISO Shift Register
DIP-16 Top View
16 Pins
Pin-Tabelle16
| Pin | Signal / Name | Typ | Alternative Funktionen |
|---|---|---|---|
| 1 | ~PL | Digital | Parallel Load (Active Low — pull LOW to load D0–D7 into register) |
| 2 | CP | Digital | Clock Pulse (rising edge shifts register one position) |
| 3 | D4 | Digital | Parallel Data Input Bit 4 |
| 4 | D5 | Digital | Parallel Data Input Bit 5 |
| 5 | D6 | Digital | Parallel Data Input Bit 6 |
| 6 | D7 | Digital | Parallel Data Input Bit 7 (MSB) |
| 7 | Q7 | Digital | Serial Data Output (non-inverted, connect to next device DS) |
| 8 | GND | Ground | System Ground (0V) |
| 9 | ~Q7 | Digital | Serial Data Output Complemented (inverted Q7) |
| 10 | DS | Digital | Serial Data Input (connects to Q7 of preceding device in chain) |
| 11 | D0 | Digital | Parallel Data Input Bit 0 (LSB, first to shift out) |
| 12 | D1 | Digital | Parallel Data Input Bit 1 |
| 13 | D2 | Digital | Parallel Data Input Bit 2 |
| 14 | D3 | Digital | Parallel Data Input Bit 3 |
| 15 | ~CE | Digital | Clock Enable (Active Low — pull LOW to allow clocking; tie LOW if unused) |
| 16 | VCC | Power | Positive Power Supply (2–6V) |